Design for testing

About: Design for testing is a research topic. Over the lifetime, 3946 publications have been published within this topic receiving 63049 citations. The topic is also known as: Design for Testability, DFT.

Progressive random access scan: a simultaneous solution to test power, test data volume and test time

Abstract: Traditional testing research for testing VLSI circuits has been confined to the use of serial scan test architecture whose origin lies in keeping the hardware overhead low. However, there has been a paradigm shift in the cost factor - the transistor cost has been dropping exponentially whereas the test cost is starting to increase. We believe that adding marginally more hardware is acceptable provided the test cost can be reduced considerably. This paper takes such a view of testing and rejuvenates the random access scan as a design for testability method that simultaneously addresses three limitations of the traditional serial scan namely, test data volume, test application time, and test power. The novelty of the progressive random access scan approach proposed in this paper lies in developing the test architecture and formulating the test application time and test data volume reduction problems. We provide a traveling salesman formulation of these problems in our test architecture setting. Experimental results show the practicality of our approach as the hardware cost components, consisting of routing and transistor count, increase only marginally compared to the serial scan approach whereas there is a dramatic decrease in test power consumption (nearly a 1000 fold decrease in average test power) as well as the test data volume and the test times are halved

From specification validation to hardware testing: a unified method

Abstract: With the great advancement in the design automation field, actual tools allow to describe hardware systems as software programs using high-level hardware description languages such as VHDL or VERILOG. Consequently, a design fault which affects the system specification can be considered as a software fault. To test the system specification against (software) design faults, we propose in this paper an adaptation of the mutation analysis, originally proposed for software testing, to test VHDL functional descriptions. The resulted test set is applied on the gate-level structure of the system to measure its capacity to uncover hardware faults such as the stuck-at faults. Heuristics to enhance the test set in order to be sufficient for testing hardware faults are presented and results are compared to traditional ATPGs. Accordingly, this paper presents a unified method for testing both the system specification and the hardware implementation.

An algorithm to reduce test application time in full scan designs

Abstract: An algorithm for generating a test with fewer test clocks for full scan designs by using combinational and sequential test generation algorithms adaptively is presented. Heuristics combining tests measures and scan strategies are introduced. The algorithm, 'Test Application time Reduction for Full scan designs' (TARF), is implemented and tested on a set of ISCAS sequential benchmark circuits. The results show that TARF achieves the same test coverage as combinational test generators but with fewer test clocks. >

Random access scan: a solution to test power, test data volume and test time

Abstract: Adherence to serial scan is preventing the researchers from investigating alternative design for test techniques that may offer larger test benefit at the cost of some what higher overhead. In this paper, we investigate the use of random access scan for simultaneous reduction of test power, test data volume and test application time. We provide an asymmetric traveling salesman formulation of these problems to minimize random access scans and the test data. Application of our method results into nearly 3/spl times/ speedup in test application time, 60% reduction in test data volume and over 99% reduction in power consumption for benchmark circuits.

Instruction-level DFT for testing processor and IP cores in system-on-a-chip

Abstract: Self-testing manufacturing defects in a system-on-a-chip (SOC) by running test programs using a programmable core has several potential benefits including, at-speed testing, low DfT overhead due to elimination of dedicated test circuitry and better power and thermal management during testing, However, such a self-test strategy might require a lengthy test program and might not achieve a high enough fault coverage. We propose a DfT methodology to improve the fault coverage and reduce the test program length, by adding test instructions to an on-chip programmable core such as a microprocessor core. This paper discusses a method of identifying effective test instructions which could result in highest benefits with low area/performance overhead. The experimental results show that with the added test instructions, a complete fault coverage for testable path delay faults can be achieved with a greater than 20% reduction in the program size and the program runtime, as compared to the case without instruction-level DfT.