Design for testing

About: Design for testing is a research topic. Over the lifetime, 3946 publications have been published within this topic receiving 63049 citations. The topic is also known as: Design for Testability, DFT.

Power reduction in test-per-scan BIST

Abstract: The input signal activities during test can be much higher than during test. Hence, it is important to reduce power consumption to avoid any failures during test. In this paper, we propose techniques to reduce power dissipations in both the combinational block and the scan chain for test-per-scan BIST. Some extra circuitry is introduced between the combinational logic and the scan chain to make the combinational block idle during the scan-in and scan-out operation, and the scan chain is re-ordered so that the number of signal transitions in it is minimized. Compared to the standard weighted random pattern (WRP) testing (without re-ordering), the number of signal transitions in the scan chain can be reduced by 43.8%. With some extra circuitry, the power dissipation in the combinational block can be reduced to less than 0.86%, compared to the standard test-per-scan BIST.

An integration of memory-based analog signal generation into current DFT architectures

Abstract: One method for the testing of mixed analog/digital integrated circuits involves the digital encoding of analog signals into an aperiodic pulse-density-modulated (PDM) serial bit stream and using it to stimulate a device under test. This paper describes a method for obtaining a short periodic approximation of the PDM pattern and identifies two methods of integrating this analog test scheme into the current digital test environment: RAM- and scan-based storage. Using such design-for-test logic as the 1149.1-1990 JTAG architecture and a typical RAMBIST controller these analog signal generation techniques can be added to digital ICs with minimal additional hardware overhead.

Defect-oriented vs schematic-level based fault simulation for mixed-signal ICs

Abstract: Escalating demand for mixed-signal Integrated Circuits has been accompanied by the need to develop efficient strategies to guarantee higher quality at lower cost. One key to achieving this is efficient production test and the utilization of Design-for-Testability (DfT). Fault simulation based test evaluation would be a major contribution towards measuring and optimizing the effectiveness of a production test. Fault simulations, however, are only useful if the underlying fault list generation approaches accurately reflect manufacturing defects-both in their probability of occurrence and in their electrical behavior. This paper evaluates and compares two fault list generation approaches and the implications on test optimization. Fault lists derived from both Inductive Fault Analysis (IFA) and a transistor fault-model are compared for a testability analysis on a self-test function for a high-performance switched-current design.

Design space exploration with A Stream Compiler

Abstract: We consider speeding up general-purpose applications with hardware accelerators. Traditionally hardware accelerators are tediously hand-crafted to achieve top performance ASC (A Stream Complier) simplifies exploration of hardware accelerators by transforming the hardware design task into a software design process using only 'gcc' and 'make' to obtain a hardware netlist. ASC enables programmers to customize hardware accelarators at three levels of abstraction: the architecture level, the functional block level, and the bit level. All three customizations are based on one uniform representation: a single C++ program with custom types and operators for each level of abstraction. This representation allows ASC users to express and reason about the design space, extract parallelism at each level and quickly evaluate different design choices. In addition, since the user has full control over each gate-level resource in the entire design. ASC accelerator performance can always be equal to or better than hand-crafted designs, usually with much less effort. We present several ASC bench marks, including wavelet compression and Kasumi encryption.