Design for testing

About: Design for testing is a research topic. Over the lifetime, 3946 publications have been published within this topic receiving 63049 citations. The topic is also known as: Design for Testability, DFT.

An Integrated Frequency Response Characterization System With a Digital Interface for Analog Testing

Abstract: Current and future integrated systems demand cost-effective test solutions. In response to that need, this work presents a very compact mixed-signal test system. It performs the characterization of the magnitude and phase responses over frequency at multiple nodes of an analog circuit. The control inputs and output of this system are digital, enabling the test of the analog components in a system-on-chip (SoC) or system-in-package (SiP) through a low-cost digital automatic test equipment. Robust and area-efficient building blocks are proposed for the implementation of the test system, including a linearized analog multiplier for accurate magnitude and phase detection, a wide tuning range voltage-controlled oscillator and a low-power algorithmic analog-to-digital converter. Their individual design considerations and performance results are presented. A complete prototype in TSMC CMOS 0.35-mum technology employs only 0.3mm2 of area. The operation of this test system is demonstrated by performing frequency response characterizations up to 130 MHz at various nodes of two different fourth-order continuous-time filters integrated in the same chip

Retiming sequential circuits to enhance testability

Abstract: This paper presents a technique to enhance the testability of sequential circuits by repositioning registers. A novel retiming for testability technique is proposed that reduces cycle lengths in the dependency graph, converts sequential redundancies into combinational redundancies, and yields retimed circuits that usually require fewer scan registers to break all cycles (except self-loops) as compared to the original circuit. The retiming technique is based on a new minimum cost flow formulation that simultaneously considers the interactions among all strongly connected components (SCCs) of the circuit to minimize the number of registers in the SCCs. Experimental results on several large sequential circuits demonstrate the effectiveness of the proposed retiming for testability technique. >

Modifying user-defined logic for test access to embedded cores

Abstract: Testing embedded cores is a challenge because access to core I/Os is limited. The user-defined logic (UDL) surrounding the core may restrict the set of test vectors that can be applied to the core. Consequently, some of the core test vectors specified by the core supplier may not be contained in the output space of the UDL that drives the core and hence cannot be justified at the core inputs. Conventional solutions to this problem involve placing multiplexers or boundary scan elements at the inputs of the core to provide test access. This can be very costly in terms of area and performance. This paper presents a new approach for providing test access to an embedded core. A procedure is described for inserting control points in the UDL to modify its output space so that it contains the specified core test vectors. The flexibility in selecting the location of the control points is used to avoid performance degradation by keeping test logic off the critical timing paths. Experimental results are shown comparing the control point insertion procedure with other approaches.

Design of reconfigurable access wrappers for embedded core based SoC test

Abstract: Testing of embedded core based system-on-chip (SoC) ICs is a well known problem, and the upcoming IEEE P1500 Standard on Embedded Core Test (SECT) standard proposes DFT solutions to alleviate it. One of the proposals is to provide every core in the SoC with test access wrappers. Previous approaches to the problem of wrapper design have proposed static core wrappers, which are designed for a fixed test access mechanism (TAM) width. We present the first report of a design of reconfigurable core wrappers which allow for a dynamic change in the width of the TAM executing the core test. Analysis of the corresponding scheduling problem indicates that good approximate schedules can be achieved without significant computational effort. Specifically, we derive a O(N/sub C//sup 2/B) time algorithm which can compute near optimal SoC test schedules, where N/sub C/ is the number of cores and B is the number of top level TAMs. Experimental results on benchmark SoCs are presented which improve upon integer programming based methods, not only in the quality of the schedule, but also significantly reduce the computation time.

Glitch-Aware Pattern Generation and Optimization Framework for Power-Safe Scan Test

Abstract: Excessive dynamic voltage drop in the power supply rails during test mode is known to result in false failures and impact yield when testing devices that use low-cost wire-bond packages. Identifying and debugging such test failures is a complex and effort-intensive process, especially when scan compression is involved. From a design cycle-tune view point, it is best to avoid this problem by generating "power-safe" scan patterns. The generation of power-safe patterns must take into consideration the DFT architecture, physical design, tuning and power constraints. In this paper, the authors propose such a framework and show experimental results on some benchmark circuits. The framework can address a non-uniform power grid and region-based power constraints. The authors show that glitching activity on nodes must be considered in order to correctly handle constraints on instantaneous peak power. The framework includes a power profiler that can analyze a pattern source for violations and a PODEM-based pattern generation engine for generating power-safe patterns.