Design for testing

About: Design for testing is a research topic. Over the lifetime, 3946 publications have been published within this topic receiving 63049 citations. The topic is also known as: Design for Testability, DFT.

Structural Fault Testing of Embedded Cores Using Pipelining

Abstract: The purpose of this paper is to develop a global design for test methodology for testing a core-based system in its entirety. This is achieved by introducing a “bypass” mode for each core by which the data can be transferred from a core input port to the output port without interfering the core circuitry itself. The interconnections are thoroughly tested because they are used to propagate test data (patterns or signatures) in the system. The system is modeled as a directed weighted graph in which the accessibility (of the core input and output ports) is solved as a shortest path problem. Finally, a pipelined test schedule is made to overlap accessing input ports (to send test patterns) and output ports (to observe the signatures). The experimental results show higher fault coverage and shorter test time.

A serial scan test vector compression methodology

Abstract: This paper presents a serial scan test vector compression methodology for the test time reduction in a scan-based test environment. The reduction is achieved by the overlapping of two consecutive vectors. Hence, the order of test vectors determines the amount of reduction in tiem. Here, two test vector ordering algorithms, depth first greedy and coalesced simple orders algorithms, have been derived, implemented, and tested. Experimental results obtained are very close to estimations by statistical analysis. >

Testing-Based Watermarking Techniques for Intellectual-Property Identification in SOC Design

Abstract: The author proposes a novel testing-based watermarking scheme for intellectual-property (IP) identification in this paper. The principles are established for the development of new watermarking IP-identification procedures that depend on current IP-based design flow. The core concept is embedding a watermark-generating circuit (WGC) and a test circuit into the IP core at the behavior design level. Therefore, this scheme can also successfully survive synthesis, placement, and routing and can identify the IP core at various design levels. This method adopts current main system-on-a-chip (SOC) design-for-test (DFT) strategies. The identity of the IP is proven during the general test process without implementing any extra extraction flow. After the chip has been manufactured and packaged, it is still easy to detect the identification of the IP provider without the need to examine the microphotograph. On real designs, our approaches entail low hardware overhead, tracking costs, and processing-time costs. The proposed method solves the IP-identification problem.

Process aggravated noise (PAN): new validation and test problems

Abstract: How the trends in circuit design are increasing the significance of noise effects, such as crosstalk and ground bounce, is demonstrated. Further aggravated by process variations, these process aggravated noise (PAN) effects must be considered as an integral part of the design validation methodology. It is shown that the validation of a design in the presence of PAN effects requires simulation at new design corners that are not typically considered during the validation of digital CMOS circuits. Furthermore, it is shown that the choice of a new design corner depends not only on the particular PAN effect under consideration, but also on the nature of the circuit. We demonstrate the need for automating the process of selecting design corners as well as test sequences for validation and outline strategies for their automation.

Design and test of mixed signal circuits: a discrete-event approach

Abstract: Due to the heavy analog nature of vehicles and the increasing use of microprocessor techniques, most circuits in automobiles nowadays carry mixed (digital and analog) signals. As complexities of these circuits increase, testability of mixed signal circuits has become an important issue that must be dealt with by both design and test engineers. A systematic approach to study testability of mixed signal circuits is urgently needed, because current ad hoc methods cannot efficiently handle increasingly complex and ever changing circuits. In this paper, we develop a uniform and systematic approach to the testability problem. The approach is based on a theory of discrete event systems. It is suitable for the following tasks: (1) checking testability of a circuit; (2) computing minimum test set (i.e., the minimum number of test conditions or test points to verify functionality); (3) assisting with circuit design for testability; (4) finding the degree of testability; (5) dividing a circuit into testable modules. >