Topic
Design for testing
About: Design for testing is a research topic. Over the lifetime, 3946 publications have been published within this topic receiving 63049 citations. The topic is also known as: Design for Testability, DFT.
Papers published on a yearly basis
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23 May 2000TL;DR: A RTL-based defect-oriented test generation methodology is proposed, for which a high defects coverage (DC) and a relatively short test sequence can be derived, thus allowing low-energy operation in test mode and enhancing the test effectiveness of classic, gate-level test generation.
Abstract: Functional test is long viewed as unfitted for production test. The purpose of this contribution is to propose a RTL-based test generation methodology which can be rewardingly used both for design validation and to enhance the test effectiveness of classic, gate-level test generation. Hence, a RTL-based defect-oriented test generation methodology is proposed, for which a high defects coverage (DC) and a relatively short test sequence can be derived, thus allowing low-energy operation in test mode. The test effectiveness, regarding DC, is shown to be weakly dependent on the structural implementation of the behavioral description. The usefulness of the methodology is ascertained using the VeriDOS simulation environment and the CMUDSP ITC'99 benchmark circuit.
39 citations
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TL;DR: The design of a versatile module test and maintenance controller (MMC) that can be implemented as a single-chip ASIC (application-specific integrated circuit) or by off-the-shelf components is presented.
Abstract: The design of a versatile module test and maintenance controller (MMC) is presented. Driven by structures test programs, an MMC is able to test every chip in a module or PCB via a test bus. More than one test bus can be controlled by an MMC, and can support several bus architectures and many modes of testing. The differences between MMCs on different modules are the test programs that they execute, the number of test buses they control, and the expansion units they use. A simple yet novel circuit, called a test channel, is used in an MMC. The MMC processor can control a test channel by reading/writing its internal registers. Once initialized by the MMC processor, a test channel can carry out most of the testing of a chip. Thus the processor need not deal with detailed test-bus control sequences since they are generated by the test channel. This strategy greatly simplifies the development of test programs. The proposed MMC can be implemented as a single-chip ASIC (application-specific integrated circuit) or by off-the-shelf components. Some of its self-test features are presented. >
39 citations
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25 Apr 2004TL;DR: A loop-back architecture, along with a novel, all-digital design-for-testability (DfT) modification that enables cost efficient testing of various defects at the wafer level, applicable to a wide range of cost-sensitive applications that use the modulation of the voltage-controlled-oscillator (VCO).
Abstract: Traditionally, radio frequency (RF) paths are bypassed during wafer sort due to the high cost of RF testing. Increasing packaging costs, however; result in a need for a more thorough wafer-level testing including the RF path. In this paper, we propose a loop-back architecture, along with a novel, all-digital design-for-testability (DfT) modification that enables cost efficient testing of various defects at the wafer level. These methods are applicable to a wide range of cost-sensitive applications that use the modulation of the voltage-controlled-oscillator (VCO). Experimental results using a Bluetooth platform and considering a variety of defects confirm the viability of the approach.
39 citations
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TL;DR: Results show that the proposed algorithm cannot only reduce the computation complexity but also shorten the time consumption, particularly useful for large-scale analog circuits.
Abstract: A novel multidimensional fitness function discrete particle swarm optimization algorithm is proposed to optimize analog test point selection. The proposed method uses fault isolation rate and the number of test points to formulate a multidimensional fitness function to search the global minimal test point set, and an elitist set is used to get more than one possible best solution in the described approach. The efficiency of the proposed method is proven by the same experiments used to verify other methods for optimal test points. Results show that the proposed algorithm in this paper cannot only reduce the computation complexity but also shorten the time consumption. It is particularly useful for large-scale analog circuits.
39 citations
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01 Jun 1988TL;DR: An automated built-in self-test (BIST) technique for general sequential logic is described, incorporated in a behavioral model synthesis system, providing automated implementation of BIST in very-large-scale-integration (VLSI) devices as well as programmable-logic-device (PLD)-based circuit packs.
Abstract: An automated built-in self-test (BIST) technique for general sequential logic is described. This approach has been incorporated in a behavioral model synthesis system, providing automated implementation of BIST in very-large-scale-integration (VLSI) devices as well as programmable-logic-device (PLD)-based circuit packs. BIST can be directly used at all levels of testing from device testing through system diagnostics. It is based on selective replacement of existing system memory elements with BIST flip-flop cells that are connected to form a circular chain, performing data compaction and test pattern generation simultaneously. Two production VLSI devices have been implemented with this automated BIST approach. In each case, the total fault coverage was in excess of 96% and the logic overhead incurred was between 9.7 and 18.9%. >
39 citations