Design for testing

About: Design for testing is a research topic. Over the lifetime, 3946 publications have been published within this topic receiving 63049 citations. The topic is also known as: Design for Testability, DFT.

Design for testability of analog/digital networks

Abstract: The testing of analog/digital integrated circuits is difficult since they allow direct access to relatively few signals. Since the probing of component pins is the fundamental chip production test technique (and possibly that of board test as well, i.e. in-circuit test), methods must be found to enhance the controllability and observability of internal signal networks. The authors provide a set of design for testability (DFT) principles that enhance their ability to test these networks when combined with the requisite analog test plans. >

An optimal time expansion model based on combinational ATPG for RT level circuits

Abstract: We present an approach to test generation using time expansion models. The tests for acyclic sequential circuits can be generated by applying combinational ATPG to our time expansion models. We performed experiments on application to partial scan designed register-transfer circuits. The results show that our approach can reduce hardware overhead and test length compared with full scan while preserving almost 100% fault efficiency.

Digital integrated circuit design system and methodology with hardware

Abstract: A method of designing an integrated circuit employs hardware testing rule checking so as to ensure hardware testability and to ensure that automated test program generation will succeed when the design cycle reaches that stage. The method calls for, first, receiving a proposed logic design defined at a functional or behavioral level; second, defining a test bench for simulating operation of the logic design, the test bench including at least one input vector for stimulating the logic design for verifying the operation of the logic design; receiving a predetermined set of one or more hardware testing rules associated with a target tester; simulating operation of the logic design using the test bench; and, prior to releasing the logic design for logic synthesis, checking the simulation for compliance with the hardware testing rule set. Preliminary checking of the design and test bench prior to synthesis can avoid costly corrections later in connection with test program generation.

The design of an adaptive on-line binary arithmetic-coding chip

Abstract: In this paper, we present a very large scale integration (VLSI) design of the adaptive binary arithmetic coding for lossless data compression and decompression. The main modules of it consist of an adaptive probability estimation modeler (APEM), an arithmetic operation unit (AOU), and a normalization unit (NU), A new bit-stuffing technique, which simultaneously solves both the carry-over and source-termination problems efficiently, is proposed and designed in an NU. The APEM estimates the conditional probabilities of input symbols efficiently using a table lookup approach with 1.28-kbytes memory. A new formula which efficiently reflects the change of symbols' occurring probability is proposed, and a complete binary tree is used to set up the values in the probability table of an APEM. In an AOU, a simplified parallel multiplier, which requires approximately half of the area of a standard parallel multiplier while maintaining a good compression ratio, is proposed. Owing to these novel designs, the designed chip can compress any type of data with an efficient compression ratio, An asynchronous interface circuit with an 8-b first-in first-out (FIFO) buffer for input/output (UO) communication of the chip is also designed. Thus, both UO and compression operations in the chip can be done simultaneously. Moreover, the concept of design for testability is used and a scan path is implemented in the chip. A prototype 0.8-/spl mu/m chip has been designed and fabricated in a reasonable die size. This chip can yield a processing rate of 3 Mb/s with a clock rate of 25 MHz.

Testing mixed signal ASICs through the use of supply current monitoring

Abstract: The authors investigate testing of mixed signal integrated circuits. Several approaches are proposed, most requiring careful partitioning of the analogue and digital sections. However, the use of supply current monitoring is applicable to both digital and analogue sections. Digital testing has been widely investigated, concentrating on quiescent I/sub ddq/ testing. Using pseudo-random binary test signals with supply current testing, high fault coverage of both catastrophic FET faults and gate oxide shorts in the analogue section is shown to be obtainable. Use of on-chip supply sensors has also been investigated. >