Design for testing

About: Design for testing is a research topic. Over the lifetime, 3946 publications have been published within this topic receiving 63049 citations. The topic is also known as: Design for Testability, DFT.

The VLSI circuit test problem-a tutorial

Abstract: Defect-free integrated circuits (IC) cannot be guaranteed by VLSI circuit manufacturers. Circuit complexity, IC defect anomalies, and economic considerations prevent complete validation of VLSI circuits. These VLSI test problems are especially acute in high-reliability designs and will only worsen as IC circuit size increases. Designers of IC, board, and system projects must be aware of the difficult engineering challenges that are involved in verifying high-quality ICs. The authors discuss these topics and emphasize the need for basic design for testability methods that must be used to alleviate these problems. >

System chip test: how will it impact your design?

Abstract: A major challenge in realizing core-based system chips is the adoption and design-in of adequate test and diagnosis strategies. This tutorial paper discusses the specific challenges that come with testing deeply embedded reusable cores supplied by diverse providers, who often use different hardware description levels and mixed technologies. The paper describes a general test access architecture for embedded cores, and covers the current standardization efforts in this domain. In addition, we give an overview of the emerging EDA developments in SOC test, and illustrate the current industrial practices by means of two case studies.

Embedded Deterministic Test Points

Abstract: There is mounting evidence that automatic test pattern generation tools capable of producing tests with high coverage of defects occurring in the large semiconductor nanometer designs unprecedentedly inflate test sets and test application times. A design-for-test technique presented in this paper aims at reducing deterministic pattern counts and test data volume through the insertion of conflict-aware test points. This methodology identifies and resolves conflicts across internal signals allowing test generation to increase the number of faults targeted by a single pattern. This is complemented by a method to minimize silicon area needed to implement conflict-aware test points. The proposed approach takes advantage of the conflict analysis and reuses functional flip-flops as drivers of control points. Experimental results on industrial designs with on-chip test compression demonstrate that the proposed test points are effective in achieving, on average, an additional factor of $2\times $ – $4\times $ compression for stuck-at and transition patterns over the best up-to-date results provided by the embedded deterministic test (EDT)-based regular compression.

Fault Tolerant QCA Logic Design With Coupled Majority-Minority Gate

Abstract: Synthesis of efficient DFT (Design for Testability) logic is of prime importance in robustly testable design of QCA based logic circuits. An ingenious universal QCA gate structure, Coupled Majority-Minority (CMVMIN) gate, realizes majority and minority functions simultaneously in its 2-outputs. This device enables area saving implementation of complex QCA logic. In the current work, we investigate cost effective DFT for QCA designs realized with CMVMIN. The fault effects at the gate outputs due to cell deposition and cell misplacement defects are characterized for concurrent testable circuit design. The effective use of unutilized outputs of CMVMIN gates, realizing a circuit, leads to the proposed fault tolerant design that may not be possible with the conventional gate structures.

Transformations and resynthesis for testability of RT-level control-data path specifications

Abstract: This paper introduces a technique to transform a given register-transfer level (RT-level) design, consisting of control logic and data path, into a functionally equivalent, minimized design which is 100% testable under full-scan at the gate level. The proposed RT-level optimization technique uses the RT-level structure and exploits the interaction between the control and the data path. Our approach maintains the RT-level design hierarchy while performing RT-level transformations of initially specified data path, followed by resynthesis of control using don't cares extracted from the data path. Experiments with several RTL benchmarks demonstrate the effectiveness of the technique in generating fully testable designs. In addition, comparison with logic-level techniques show the advantages of the proposed technique as an optimizing tool to produce circuits with reduced area and delay. >