Design for testing

About: Design for testing is a research topic. Over the lifetime, 3946 publications have been published within this topic receiving 63049 citations. The topic is also known as: Design for Testability, DFT.

On-line testable logic design for FPGA implementation

Abstract: In recent years, a number of logic design techniques for look-up table (LUT) based FPGAs have been proposed. However, none of these address issues such as fault detection or testability. This paper presents an algorithm which maps optimized Boolean expressions into look-up table based FPGAs. This mapping automatically incorporates testability features into designs, allowing on-line detection of faults within a FPGA. This is accomplished by utilizing a unique set of cells to implement a design. These cells operate on the premise of a two-rail checker, thus producing both the normal and complemented output when a cell is operating correctly, and two outputs of the same value in the presence of a fault. Faults generated in an intermediate cell is propagated to the final outputs, thus allowing on-line testability of a FPGA-based logic system.

Layout-dependent fault analysis and test synthesis for CMOS circuits

Abstract: An arithmetic approach to extract the potential physical defects from the specific circuit layout of an integrated circuit is proposed. The defects subsequently are transformed into circuit faults and weighted according to their likelihood of occurrence. Based on these open and short faults extracted from CMOS layouts, an automatic test pattern generator is implemented. The test synthesis of some combinational CMOS benchmark circuits illustrates the superiority of the CMOS fault models and their application to test pattern generation as compared with the classical stuck-at fault models. >

Bridging fault extraction from physical design data for manufacturing test development

Abstract: In this paper we explore the process of extracting potential bridging fault sites from the physical design database for VLSI devices by using standard extraction tools for fringe and overlap capacitance. We then use the extracted capacitance to create a list of potential bridging fault sites ordered to reflect the relative probability of a bridging fault occurring at each site. As a result, potential bridging fault sites can be rank-ordered for manufacturing test development such that the most likely site can be targeted first. In this way we improve the overall efficiency and effectiveness of the test development process. We have implemented this technique for the Delta 39K/sup TM/ series of complex programmable logic devices by Cypress Semiconductor and describe the results obtained.

Enhancing Delay Fault Coverage through Low Power Segmented Scan

Abstract: Reducing power dissipation during test has been an active area of academic and industrial research for the last few years and numerous low power DFT techniques and test generation procedures have been proposed. Segmented scan (Whetsel, 2000) and (Lee et al., 2004) has been shown to be an effective technique in addressing test power issues in industrial designs (Saxena et al., 2001). To achieve higher shipped product quality, tests for delay faults are becoming essential components of manufacturing test. This paper demonstrates, for the first time, that segmented scan facilitates increased delay fault coverage without degrading the reduction of the switching activity obtained by segmented scan. The increased transition delay fault coverage is achieved through careful selection of the capture cycle application. Experimental results on larger ISCAS-89 benchmarks show that using three segments, on average, fault coverage using launch off capture can be increased by about 5.4% while simultaneously reducing the peak switching activity caused by capture cycles by over 30%

SOC Test Architecture and Method for 3-D ICs

Abstract: 3-D integration provides another way to put more devices in a smaller footprint. However, it also introduces new challenges in testing. Flexible test architecture named test access control system for 3-D integrated circuits (TACS-3D) is proposed for 3-D integrated circuits (IC) testing. Integration of heterogeneous design-for-testability methods for logic, memory, and through-silicon via (TSV) testing further reduces the usage of test pins and TSVs. To highly reuse pre-bond test circuits in post-bond test, an innovative linking mechanism shares TSVs and test pins of the 3-D IC. No matter how many layers are there in the 3-D IC, a large portion of TSVs and test pins is reserved for data application. Therefore, smaller post-bond test time is expected. A test chip composed of a network security processor platform is taken as an example. Less than 0.4% test overhead increases in area and time between 2-D and 3-D cases. Compared with the instinctively direct access, TACS-3D reveals up to 54% test time improvement under the same TSV usage.