Design for testing

About: Design for testing is a research topic. Over the lifetime, 3946 publications have been published within this topic receiving 63049 citations. The topic is also known as: Design for Testability, DFT.

Test point insertion for an area efficient BIST

Abstract: We present a new cost based method for the insertion of test points into sequential circuits. It is especially suited for the design of an area efficient BIST using pseudorandom patterns. Testability analysis is used to detect areas of poor testability and estimate the benefit of test points. The designer can trade this benefit against increased area. Experimental results show that small sets of test points are sufficient to reach a fault coverage greater than 99%.

Native mode functional self-test generation for Systems-on-Chip

Abstract: With the rapid increase in the functionality of a single chip, the generation of high quality manufacturing tests which can be applied at-speed has become a serious issue. The problem is further compounded with an increasing level of integration in the case of Systems-On-Chip (SOCs), for which existing test generation tools are inadequate. Many of the peripherals in a SOC design may not include testability features, which renders conventional design for testability (DFT) approaches ineffective. Functional tests applied at-speed in the native mode of a microprocessor have been shown to be effective in detecting realistic defects. A novel approach to adopt this strategy to generate test patterns for SOCs is presented in this paper. This approach utilizes the core processor's instruction set to test its own functionality and that of the peripheral components. A SOC based on a model of the Intel 8085 processor is used to show the effectiveness of this approach.

Intelligent reasoning assistant for incorporating manufacturability issues into the design process

Abstract: This paper describes an integrated Intelligent Reasoning Assistant (IRA) as an approach to incorporate manufacturability issues into the design process. By using a series of pre-established geometric features available from a CAD system and manufacturing knowledge captured from experienced design and manufacturing personnel, the proposed model is used to recommend feasible manufacturing process sequences and design changes that enhance design manufacturability early in the conceptual design stage. The used Design For Manufacturing (DFM) approach assumes that incorporating manufacturing issues into the design process is not a serial decision method, rather, it is a process with multiple parallel interactions from origination of a conceptual design to direct linkage with manufacturing parameters. Although the emphasis of this research has been focused on part designs which are metal machining intensive, it is believed that the described approach can be generalized to other manufacturing environments.

Optimal Seguencing of Scan Registers

Abstract: Due to the high cost of test equipment, reducing the test time of a device is important. Scan designs require a large test application time. We present a methodology to construct a single scan chain that provides dramatic reductions in test application time. The main idea as t o order the scan registers in the chain so as to enable easy access to registers that are frequently used. In conjunction with a novel test application scheme, we provide an algorithmic technique to generate single chain configurations that minimize the test time. Implementation results highlighting the advantages of the proposed methodology are presented.

Implementing macro test in silicon compiler design

Abstract: A testability strategy for a complex VLSI device that is implemented in the Piramid digital-signal-processor silicon compiler is presented. The macro test method proposed supports built-in self-test, scan test, restricted partial scan, and test-control logic at various levels in the design hierarchy. The strategy uses techniques such as a macro test plan, transfer information, and intermediate vector storage. The overhead from adding testability is only 10% of the total area and test-program generation is done with 100% fault coverage in a very short time, since there is no need for global test-pattern generation. A set of tools that guide the testability implementation from design to the final test program is described. >