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Design for testing

About: Design for testing is a research topic. Over the lifetime, 3946 publications have been published within this topic receiving 63049 citations. The topic is also known as: Design for Testability, DFT.


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Journal ArticleDOI
TL;DR: A design-for-test method that permits at-speed testing is introduced based on probe point insertion for improved observability, and it requires enhancements to an existing sequential circuit fault simulator.
Abstract: Some recent studies show that an at-speed sequential or functional test is better than a test executed at lower speed. Design-for-testability approaches based on full scan, partial scan or silicon-based solutions such as Crosscheck achieve very high stuck-at fault coverage. However, in all these cases, the tests have to be applied at speeds lower than the operation speed of the circuit. In this paper, a design-for-test method that permits at-speed testing is introduced. The method is based on probe point insertion for improved observability, and it requires enhancements to an existing sequential circuit fault simulator. Faults that can be activated but not detected at existing primary outputs are targeted. A minimal set of probe points is selected to detect these faults, and the probe points are compressed to one or two output pins using exclusive-OR trees. The issue of aliasing of fault effects is addressed. Improvements in fault coverage were made for all 17 of the ISCAS89 sequential benchmark circuits studied. Fault coverages between 99% and 100% were obtained for seven circuits, and 100% ATG effectiveness was achieved on all but two circuits. >

30 citations

Journal ArticleDOI
TL;DR: D1*CA has been proposed as an ideal test machine which can be efficiently embedded in a finite state machine to enhance the testability of the synthesized design.
Abstract: The paper reports some of the interesting properties and relationships of a nongroup cellular automata (CA) and its dual. A special class of nongroup cellular automata denoted as D1*CA is analytically investigated. Based on such analysis, D1*CA has been proposed as an ideal test machine which can be efficiently embedded in a finite state machine to enhance the testability of the synthesized design. A state encoding algorithm has been formulated to embed the D1*CA based test machine in the synthesized FSM while minimizing the hardware overhead. The unique state transition properties of D1*CA are then used in designing an easy testing scheme for the FSM. Experiments on FSM benchmarks have shown that the scheme achieves 100% coverage of all single stuck at faults at the cost of hardware overhead and circuit delay that are comparable, if not better, to that incurred for scan path based designs. However, the major advantage of the scheme is the significant reduction of test time overhead due to integration of an embedded test machine in the design at the synthesis phase.

30 citations

Proceedings ArticleDOI
01 Oct 1987
TL;DR: Based on this design for testability approach, parallel testing algorithms for CAMs and RAMs are developed for a broad class of pattern sensitive faults and the resulting test procedures are significantly more efficient than previous approaches.
Abstract: This paper presents a design strategy for efficient and comprehensive parallel testing of both Random Access Memory (RAM) and Content Addressable Memory (CAM). Based on this design for testability approach, parallel testing algorithms for CAMs and RAMs are developed for a broad class of pattern sensitive faults. The resulting test procedures are significantly more efficient than previous approaches. For example, the design for testability strategy allows an entire w word CAM to be read in just one operation with a resulting speed up in testing as high as w. In the case of an n bit RAM, the improvement in test efficiency is by a factor of O(√n). The overall reduction in testing time is considerable for large size memories.

30 citations

Proceedings ArticleDOI
Mohamed Azimane1, A. Majhi1
25 Apr 2004
TL;DR: It is demonstrated that the fault coverage of the resistive open defects in the memory address decoders are not completely covered by applying the well-known March tests and special test pattern sequences published in the literature.
Abstract: Intra-gate resistive open defects not only cause sequential behaviour in CMOS memory address decoders, but also lead to delay behaviour. This paper evaluates the fault coverage of the resistive open defects in the memory address decoders. It shows that both the strong and the weak open defects are not completely covered by applying the well-known March tests and special test pattern sequences published in the literature. We demonstrate that the fault coverage is increased by varying the duty cycle of the internal clock of the address decoder. For the self-timed memories, we introduce a simple DFT technique to control the duty cycle of the internal clock which activates/deactivates the word lines. Using defect-oriented test, we also created a fault dictionary based on the defect location, transistor types, the terminal name and also the faulty behaviour. The fault dictionary in combination with the bit-map fail data will facilitate the localization of the open defects.

30 citations

Proceedings ArticleDOI
26 Oct 2004
TL;DR: The main industry test trends and recent innovations in testing integrated circuits as they are applied within Philips are described.
Abstract: New process technologies, increased design complexity, and more stringent customer quality requirements drive the need for better test quality, improved test program development, and faster ramp-up at overall lower product cost. In this paper we describe the main industry test trends and recent innovations in testing integrated circuits as they are applied within Philips.

30 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202314
202232
202119
202022
201945
201859