Showing papers on "Digital electronics published in 1968"

An approach to the implementation of digital filters

Abstract: An approach to the implementation of digital filters is presented that employs a small set of relatively simple digital circuits in a highly regular and modular configuration, well suited to LSI construction. Using parallel processing and serial, two's-complement arithmetic, the required arithmetic circuits (adders and multipliers) are quite simple, as are the remaining circuits, which consist of shift registers for delay and small read-only memories for coefficient storage. The arithmetic circuits are readily multiplexed to process multiple data inputs or to effect multiple, but different, filters (or both), thus providing for efficient hardware utilization. Up to 100 filter sections can be multiplexed in audio-frequency applications using presently available digital circuits in the medium-speed range. The filters are also easily modified to realize a wide range of filter forms, transfer functions, multiplexing schemes, and round-off noise levels by changing only the contents of the read-only memory and/or the timing signals and the length of the shift-register delays. A simple analog-to-digital converter, which uses delta modulation as an intermediate encoding process is also presented for andio-frequency applications.

Introduction to switching theory and logical design

Abstract: Provides the knowledge and skills that are basic to all digital system design. Solid foundation of theory permits development of systematic design procedures. Presents classical methods, such as Karnaugh maps. Quine-McCluskey minimization. Mealy and Moore circuits, state-table minimization, hazard-free asynchronous designs, etc. This edition features design with MSI circuits, including PLA's, and register transfer (state machine) approaches to sequential system design.

Fault Testing and Diagnosis in Combinational Digital Circuits

Abstract: —he problem of designing test schedules for the testing or diagnosis of a small number of nontransient faults in combinational digital circuits (switching networks) is considered in detail. By testing and diagnosis we mean the following: 1) detection of a fault, 2) location of a fault, and 3) location of a fault within the confines of a prescribed package or module. It is shown that minimal test schedules can be readily derived–using procedures already worked out for solving certain problems in pattern recognition and switching theory–under the assumption that the selection of the test inputs in the schedule is independent of the response of the circuit under test. When this assumption is not made, it is shown that much shorter test schedules are sometimes possible, and procedures are offered for obtaining good ones. Finally, the general status of diagnostics for digital circuits is reviewed and evaluated, and specific problems remaining to be solved are described.

Digital principles and applications

Abstract: From the Publisher: The fifth edition of Digital Principles and Applications is completely reorganized . It is written for the individual who wishes to learn the principles of digital circuits and then apply them to useful, meaningful designs. The material in this book is appropriate for an introductory course in digital logic in either a computer or an electronics program. It is also appropriate for 'self-study' and as a 'reference' for individuals working in the field.

A Mathematical Model Characterizing Four-Phase MOS Circuits for Logic Simulation

Abstract: —Four-phase MOS circuits exhibit many peculiar features not observed in other families of logic circuits. In this paper, a mathematical model which characterizes the circuits is presented for logic simulation. It is shown that this model enables us to develop a computer program which can rapidly and efficiently verify and evaluate the logic design of the circuits.

Graphical data processor

Abstract: A digital and analog signal responsive processor generates a visible display of alphanumerics, halftone, or vector information. The processor includes logic circuits for developing dynamic deflection fields in a display cathode-ray tube in response to a sequence of digital codes unique for a particular alphanumeric symbol such that the tube''s electron beam is moved or scanned substantially only over the plurality of linear areas of the tube''s screen which will collectively display the desired symbol. Additional circuitry is included to generate vectors of any length either at a uniform deflection velocity or during a uniform period of time. In addition, digital circuits are present which may reproduce halftone configurations in a dot-by-dot manner. Beam intensity and focus registers permit the alteration of these qualities of the electron beam as desired.

High speed digital circuits

Abstract: Apparatus is provided in digital data equipment for transferring a binary signal to a flip-flop, and deriving therefrom a buffered output signal representing the state into which said flip-flop is being switched by anticipation means coupling the input terminal of the flip-flop to a buffer amplifier driven by the flip-flop. A multibranch, multistage selector tree is employed to selectively couple one of a number of binary signals to the flip-flop. The anticipation means and selector tree overcome and minimize the limitations in switching speeds inherent in such apparatus implemented with insulated-gate, field-effect transistors in an integrated circuit. Switching speed of the flip-flop is increased by the combination of (1) a push-pull arrangement such that when a binary signal is applied to one side the complement of the binary signal is applied to the other side, and (2) an anticipation circuit temporarily shunting current around a load resistor in series with a given one of two cross-coupled active elements.

Comments on "An Algorithm for Synthesis of Multiple-Output Combinational Logic"

Abstract: —The principal synthesis example of Schneider and Dietmeyer's paper [1] is examined by applying a new synthesis algorithm. The minimum NOR gate realization thus obtained is used to illustrate the nonoptimality of their approach and to question their definition of delay. Arguments are advanced for synthesis with simple modules.

Properties of modular multifunctional computer networks.

Abstract: : The report presents results on a first project covering research on the design of modular multifunctional logic networks. The objective of the research is the development of design techniques for general logical nets made up of modules constrained in various ways or satisfying certain criteria. Module complexity, terminal pin count, and signal delay through the network are among these criteria. Specific subjects treated in this report are logic partitioning, the design of modular logic networks with minimum delay, universal connecting networks and canonical sequential circuit modules. (Author)

DTPL all-magnetic logic networks

Abstract: The design and principles of operation of two-layer domain tip propagation logic (DTPL) set-reset and complementing flip-flops are described. These magnetic thin film devices demonstrate how the inherent delay in the propagation of channeled domain tips together with the basic DTPL logic elements (inhibit gates, fan-outs, crossovers, film-film transfers, and magnetic diodes) permit logic operations to be performed in a unique manner. Peculiar to the flip-flop devices is the fact that specific channels are continuously switched and reset by a fixed pulse sequence, although the overall network may be considered as existing in a given stable state. A ripple-carry binary counter constructed by interconnecting several similar complementing flip-flop (binary counter) stages and DTPL AND gates in a single two-layer structure is discussed.

FORTRAN simulation of digital logic

Abstract: The software described in this paper was created to aid engineering students verify the correctness of the design of digital logic systems. The verification consists of comparing a truth table generated by the simulation with the truth table desired. The software is written in FORTRAN because computers with FORTRAN compilers are widely available both to students and practicing engineers. The digital logic is defined in terms of actual hardware, rather than in terms of the classical AND, OR, and NOT functions. This feature makes it easy to write the simulation program directly from a hardware logic diagram. Thus the design is verified at the hardware level, rather than at the classical logic level. The implementation described is in terms of logic hardware produced by the Digital Equipment Corporation, but the hardware produced by any manufacturer can be described in similar terms. The method of simulation is applicable to a wide variety of both combinational and sequential logic. The restriction is that the operation of the logic system can be described by a sequence of decisions which are independent of subsequent decisions. For example it is not convenient to simulate the interconnection of two NAND gates for operation as a FLIP-FLOP. Other cases of feedback around several logic stages may also cause problems. This software is not concerned with aiding in minimization of the logic structure. The nature of the formulation of the simulation lends itself to automatic checking for fan-in or fan-out limitations, but this also is not the concern of this paper. The operation of the logic is assumed to be independent of propagation delays which there fore are not simulated. This method of simulation has been used to verify student designs for a pipeline control system, a digital message switching system, and a printer control system for a digital computer.

Use of a capacitive load in m.o.s. dynamic logic

Abstract: This letter proposes a new form of integrated m.o.s. dynamic logic based on an invertor comprising a single m.o.s.t. and a load capacitor. A compact digital delay line is described consisting of pairs of invertors operating from two clock phases. The technique is briefly compared with other dynamic approaches.

Transistor-tunnel-diode ternary-logic circuits

Abstract: Two new basic circuits for ternary-logical operations are described. Analogue simulation and experimental measurements confirm that the switching speeds of the ternary circuits can be comparable with those in similar binary circuits. It is concluded that a marginal improvement in processing rate may be achieved with ternary logic using transistor-tunnel-diode logic circuits.

A wide-range linear delay circuit†

Abstract: A wide-range linear delay circuit is described. Such circuits have wide applications. The present circuit, which has excellent temperature stability, employs a compensated bootstrap circuit for generation of a linear ramp waveform and a regenerative Schmitt triggor comparator. The circuit provides good performance and sharp waveforms which may be used for triggering other digital circuits directly.

An improved automated Nyquist plotting method using digital logic

Abstract: The motivation for the work presented here was a desire to obtain a method for automatic construction of Nyquist plots for classroom demonstration. The proposed technique may be implemented on most modern portable analog machines with some patchable logic. The idea of plotting Nyquist diagrams is not new1,2&dquo;i,.L5; however, the present method offers several advantages in terms of analog hardware requirements and in automation.