Showing papers on "Digital electronics published in 1969"

Computer-Aided Design: Simulation of Digital Design Logic

Abstract: In the ever-increasing trend to relieve man of time consuming menial tasks via automation, the digital logic designer's tasks have come under study. Various phases of this work are now being performed by computers. One of these phases, simulation of digital designs, is the topic of this paper.

Multiple signal level high-speed logic circuit device

Abstract: A multiple signal level high-speed logic circuit device wherein the logic gates within a block operate under both small- and high-logic signal swings through a direct coupling configuration. The small logic signal swing is supplied from a low-voltage electric source, and the interconnections between the respective blocks are made through voltage-level converting circuits which use PN-junction level shifts.

Computer Reduction of Two-Level, Multiple-Output Switching Circuits

Abstract: An algorithm which reduces the number of gates and connections (diodes) in two-level, multiple-output combinational logic networks is presented and compared with conventional minimization procedures.

Current-mode circuits for ternary-logic realisation

Abstract: High-speed current-mode circuits for the realisation of ternary combinational logic expressions are described.

Transition Logic Circuits and a Synthesis Method

Abstract: A transition signal is a change of binary level, either from 0 to 1 or from 1 to 0, regardless of the direction. It is often more convenient to describe a switching circuit in terms of level transitions, and a circuit with at least one input variable represented as a transition signal is called a transition logic circuit. Transition logic circuits are essentially level sequential circuits and, as such, Huffman's synthesis method can be applied. However, Huffman's synthesis rapidly becomes too laborious as the number of transition variables increases. The first part of this paper presents a synthesis approach which is simpler than Huffman's in such cases, although its applicability is more limited. In this approach, one considers a level transition as if it were a pulse, and then synthesizes the circuit following the standard pulse sequential circuit synthesis method. Circuits are constructed from two basic transition logic elements, the G element and the M element, together with ordinary gates.

Baseband pulse code modulation system

Abstract: Pulse code modulation system for reducing bandwidth in which voice signal input is compressed, limited, filtered into frequency channels, all of which are converted to the same baseband frequency and are fed to a time sharing multiplexing circuit followed by an analog to digital circuit for transmission. The digital signal is received, converted to analog, demultiplexed, demodulated to voice frequency channels and bandpass filtered. The number of channels applied to the time sharing circuit can be reduced by common band occupancy quadrature carrier methods and then converted to baseband.

Fault location in cellular arrays

Abstract: Testing of complex integrated cellular logic circuits fabricated using LSI techniques has become a source of concern to users and manufacturers. Since an economically feasible solution to testing problems is not visible for the complex arrays contemplated for the near future, manufacturers have acknowledged the seriousness of the problem. Currently some observers believe that LSI cannot be tested because general procedures for testing and diagnosing digital circuits are applicable to small networks of approximately 30 gates, while cellular arrays are contemplated as containing hundreds or thousands of gates on one chip. However, if arrays are constrained to be in a cellular form, then testing problems can be simplified and test schedules can be produced which use the interconnection structure of cellular arrays.

Design of Servo Controller for Flying Shear Machine Based on ARM and FPGA

Abstract: The flying shear machine is an important control equipment on the production line, its performance will directly affect the productivity, the quality and the qualified rate of the products. In this paper, the control problem of flying shear machine is taken as the research subject, it discusses the structure of servo controller of flying shear machine, puts forward the core control scheme based on the LPC2294 microprocessor of ARM and the EP2C8Q208N of the field programmable device, designs the hardware circuit of the servo system which includes the peripheral circuit of ARM (the power supply circuit, serial communication circuits, JTAG interface circuits, etc.), the three-phase full-bridge inverting power driver circuit, the current detection circuit and the location detection circuit. In this paper, the functions of the multiple frequency and phase discrimination loop and the function of the position loop are achieved by the FPGA. Data exchange between the FPGA and ARM is achieved through dual-port RAM, while the functions of position loop, speed loop and current loop by programming. In this paper, it takes full advantage of the rich hardware resources of FPGA and the powerful computing capability of ARM, combines the advantages of each other to ensure the rapid and flexibility. ARM processor is used as the core Controller of the Servo system, which can play its high-speed computing and programming capabilities to implement the complex real-time control algorithm and improve the control system performance. On the other hand, because of the large number of control functions and peripheral interface circuits, the use of FPGA can effectively reduces the volume of the system, the computational load on the processor and the complexity of the peripheral digital circuits, thus, all of these practices simplify the design of the hardware and software and improve the reliability and stability of the system.

Threshold Gate Building Blocks

Abstract: The problem of choosing a standard circuit package with which to realize a given logic design can be solved for threshold logic design by the use of majority gates. However, the use of asymmetric threshold gates allows substantial improvements in the amount of logic done per signal pin of the circuit package. Examples are given, illustrating savings in logic design effort, total cost of integrated circuit packages, and total cost of printed circuit boards.

Toward an algebraic theory of the analysis and testing of digital networks.

Abstract: Logic networks of Boolean analogs analyzed by algebraic signal flow theory, introducing variational derivative for test detection in combinational and sequential networks

Comments on "Fault Testing and Diagnosis in Combinational Digital Circuits"

Abstract: To be of general value, a digital fault diagnosis method must be able to handle intermittent and multiple faults.

A method of automatic fault-detection test generation for four-phase MOS LSI circuits

Abstract: To Determine Whether an integrated digital circuit is working properly, one may apply to the circuit a set of well-devised test sequences and compare the resultant outputs with the corresponding correct outputs. Any discrepancies indicate the presence of a fault. The main task here is to find a set of test sequences which can detect the presence of any prescribed fault in the circuit. This test generation problem will become formidable for large scale integrated arrays, since large number of logic circuits may be contained in an array with a limited number of exterior terminals.

Computer-aided logic design on the TX-2 computer

Abstract: A set of programs has been developed to aid in the design, testing, and documenting of logic circuits. The user can input logic descriptions by freehand sketching logic diagrams, or he can enter gate connectivity descriptions via a keyboard. Both input forms are then transformed into an internal data structure which can serve as input to logic simulation and test generation programs. Good documentation is encouraged by permitting easy editing and updating of drawings with a TX-2 graphics console which consists of a conventional oscilloscope and an input tablet. A Lincolnwriter is available for typed input and output.

A complementary MOS (CMOS) NAND/NOR Gate

Abstract: Schematic diagrams of a high-speed logic block in two slightly different forms for mass fabrication, using complementary MOSFET components, are given. Depending upon the polarity of the logic, a circuit is either a NAND/NOR or and AND/OR circuit.

An Approach to the Implementation of Digital Filters

Abstract: An approach to the implementation of digital filters is presented that employs a small set of relatively simple digital circuits in a highly regular and modular configuration, well suited to LSI construction. Using parallel processing and serial, two's-complement arithmetic, the required arithmetic circuits (adders and multipliers ) are quite simple, as are the remaining circuits, which consist of shift registers for delay and small read-only memories for coefficient storage. The arithmetic circuits are readily multiplexed to process multiple data inputs or to effect multiple, but different, filters (or both), thus providing for efficient hardware utilization. Up to 100 filter sections can be multiplexed in audio-frequency applications using presently available digital circuits in the medium-speed range. The filters are also easily modified to realize a wide range of filter forms, transfer functions, multiplexing schemes, and round-off noise levels by changing only the contents of the read-only memory and/or the timing signals and the length of the shift-register delays. A simple analog-to-digital converter, which uses delta modulation as an intermediate encoding process is also presented for audio-frequency applications.

Distributed Redundancy in Two-Layer Threshold Logic Networks

Abstract: This paper contains a description of a method which can be used to select redundant threshold logic units on the basis of system considerations rather than the duplication of existing units. This mathematical technique consists of iteratively selecting redundant threshold logic units for the first layer of a two-layer threshold logic network. Use of the technique is illustrated in the solution of simple problems, and it is shown that fewer units are required for single error correction than would be needed if existing units were duplicated.

An integrated logic gate with subnanosecond propagation delay as a system element

Abstract: Subnanosecond propagation delays in a system environment have been achieved using beam-lead silicon integrated-circuit chips assembled on ceramic substrates. The basic gate design and performance of a multi-chip logic circuit will be discussed.

R69-24 Universal Logic Circuits and Their Modular Realizations

Abstract: The integrated circuit technology is still in the process of growth and evolution. The full impact of this technology on future logical design methods is yet to come. At this point one can only wonder whether the future digital circuits will be designed in the form of strictly cellular arrays or in the form of IC circuit packages of standard "cell types" with customized metallization interconnection, or a hybrid combination of these together with cellular or noncellular "programmable logic arrays." Whatever might be the form, it seems rather certain that a basic problem common to all these approaches is the problem of designing complex logical building blocks. These blocks become the basic cells of the cellular arrays, the basic "functional units" for the customized interconnection schemes, and determine the terminal control signal sets in the programmable logic arrays. Yau and Tang have addressed themselves to this important problem without specifically stating these motivations in their paper.