Showing papers on "Digital electronics published in 1972"

A New Representation for Faults in Combinational Digital Circuits

Abstract: A new representation for faults in combinational digital circuits is presented. Faults that are inherently indistinguishable are identified and combined into classes that form a geometric structure that effectively subdivides the original circuit into fan-out-free segments. This fan-out-free characteristic allows a simplified analysis of multiple fault conditions. For certain circuits, including all two-level single-output circuits, it is shown that the detection of all single faults implies the detection of all multiple faults. The behavior of any circuit under fault conditions is represented in terms of the classes of indistinguishable faults. This results in a description of the faulty circuit by means of Boolean equations that are readily manipulated for the purpose of fault simulation or test generation. A connection graph interpretation of this fault representation is discussed. Heuristic methods for the selection of efficient tests without extensive computation are derived from these connection graphs.

Multiple level associative logic circuits

Abstract: Disclosed are universal associative logic circuits for use in designing logic systems. The logic circuits comprise an array of logic elements interconnected in a preselected configuration to implement logic in factored and unfactored form by generating single Boolean functions and complex groups of such functions having single and multiple outputs through multiple levels of combinational logic providing electrical responses to signals applied to the circuit and to signals generated within the circuit. Sequential logic functions are generated by interconnecting the logic elements to form storage elements.

Electrically programmable logic circuits

Abstract: Disclosed are universal associative logic circuits for use in designing digital systems. The logic circuits comprise an array of storage cells interconnected to form a final circuit configuration which can be electrically altered to make possible the generation of a plurality of logic functions which may be specified after fabrication of the circuit. Programming means are provided to configure the circuit so that it can generate signals representative of a required Boolean function or functions, each function having a single or a multiplicity of output signals and including both combinational and sequential logic forms.

A simple charge regenerator for use with charge-transfer devices and the design of functional logic arrays

Abstract: An inverting binary-charge regenerator for use with new charge- transfer devices (charge-coupled and integrated MOS bucket brigade) is described. This simple element requires an area approximately that of one bit in the register and is driven by the transfer pulses. Its uses with these shift registers in various configurations, which are described, make possible even larger functional devices. These uses include regeneration in serial memories, performing logic operations such as NAND and NOR involving the bit trains in several registers, and performing fixed counts and sequential addressing of other circuit elements.

Block and track method for automated layout generation of MOS-LSI arrays

Abstract: An automated layout program with a block and track concept will be described. The program, which takes logic descriptions, can generate composite-patterns for single-chip calculator MOS-LSI arrays within 600 seconds computing time with manual-comparable chip areas.

Method and apparatus for high speed digital circuit testing

Abstract: A complex digital circuit system such as a medium or a large scale integrated circuit is tested dynamically and functionally. The circuit is energized repeatedly with different sets of input signals and output signals are compared with standards. The sets of input signals successively energize the circuit at a rate of the same order of magnitude as the rate of intended operation of the circuit and the sets define a pseudo-random sequence in which each set is different. The sequence of test signals is conveniently produced by a multistage shift register having feedback loops structured and controlled to produce the particular sequence, the beginning and end of any given sequence being predetermined by a computer or operator.

A computer-based-design approach to partitioning and mapping of computer logic graphs

Abstract: A system of design automation computer programs is described which is capable of assigning blocks of a logic design to modules so as to satisfy certain constraints specified on the assignment System features which enable designer-computer cooperation are discussed, and quality of solutions obtained with the system are compared to manual solutions for the same tasks Three conclusions are reached First, these computer programs make it possible to perform partitioning and mapping experiments which were not possible before Second, for one-level partitions (eg, logic gates on chips), highly automatic solutions obtained by the system are at least as good as manual solutions and are less costly to obtain Third, for multilevel partitions (eg, logic gates on chips on cards) or for mappings, the solutions obtained with the program are again at least as good as manual solutions; furthermore, the system allows a designer to try more alternatives than he could manually, so that he can trade off the time and cost of trying additional alternatives against the value of a better solution

Binary/bcd arithmetic logic unit

Abstract: Two integrated circuit read-only-memory packages are interconnected with flip-flops and gates to form an arithmetic logic unit for performing arithmetic and logic operations in either a one-bit serial binary mode or a four-bit parallel binary-coded-decimal mode.

Solid state circuits for and method of simulating relay logic

Abstract: Logic circuits adapted to be connected in prescribed configurations are provided to form solid-state logic systems whereby the circuits directly replace and simulate relay coils and contacts to systematically generate signals representative of the operation of relays.

Circuit for modifying a train of pulses

Abstract: A digital circuit for modifying a train of a finite number of pulses has, in a most direct approach, means for deleting selected pulses from the initial pulses of the train and from the final pulses of the train. The circuit has particular utility in driving stepping motors.

A Digital Echo Suppressor for Satellite Circuits

Abstract: An echo suppressor that is composed solely of digital logic circuits and based on a digital voice detector [1] has been designed The unit is simple and requires no adjustment Its basic application is to the SPADE [2] PCM channel, although it can be adapted to work with other systems Results of initial subjective tests are included

Computer aided logic design

Abstract: This paper describes an interactive computer-aided design system which converts a state table description of a small scale synchronous digital system into a logic diagram. The input to the design programs is a State Table and a Unit Control Table that is generated by another design automation program. The State Table sequences the operations of the system. The Unit Control Table describes the operations that are to be performed on the defined units of the digital system and the conditions under which the operations are to be performed. The output of the design system is a detailed logical design of the control logic of the digital system. The output is in the form of an interconnection diagram that can be read by a digital hardware simulation program.The Computer-Aided Logic Design (CALD) System is interactive to allow the designer to change various parameters and generate many different logic designs for any particular State Table. The user may specify the state assignment, the type of memory element, and the maximum allowed gate fan-in. CALD assists the designer in performing State Table reduction and generates the state assignment at the users option. The tabular description of the digital machine is translated into a Boolean description resulting in a set of cannonical form Boolean equations in sum of product form. Memory element application equations are generated. Boolean equation minimization is performed followed by a factoring routine to enforce the fan-in constraint. The equations are then translated into a logic diagram.The CALD system is implemented in FORTRAN and running on a mini-computer with 8K of core.

Logic and memory applications of the Schottky-gate Gunn-effect digital device

Abstract: Some fundamental experiments on several basic logic and memory devices including an inhibitor and a shift register were performed, using a few planar-type Schottky-gate Gunn-effect devices and resistors in simple circuits.

Complementary transistor-transistor logic (CT/sup 2/L)-An approach to high-speed micropower logic

Abstract: A new approach to micropower integrated circuits has been developed and is called complementary transistor-transistor logic (CR/SUP 2/L). This logic combines the inherent low standby power of a complementary inverter with the high speed of the T/SUP 2/L-type input. Results of the monolithic fabricated circuits are presented.

Synchronous sequential controller for logic outputs

Abstract: Medium scale integrated circuits and logic gates are connected to provide sequential output instructions, responsive to a predetermined sequence of logic states contained in a decoder, and in synchronization with clock pulses.

Radiation Models for Digital Integrated Circuits

Abstract: The effort to be described had as its objective the development of new techniques to define simplified models of digital integrated circuits suitable for use with the SCEPTRE or similar computer programs. These models were required to account for normal electrical performance as well as performance in an environment of ionizing and/or neutron radiation. Techniques were established to derive models capable of representing both the radiation effects and the first order transient response of the microcircuits as system components for many different kinds of digital integrated circuits. A "black-box" approach was employed to achieve the desired results.

Control logic circuit for analog charge-transfer memory systems

Abstract: The operation of analog memory systems utilizing semiconductor charge-transfer devices is controlled by a control logic circuit including clock control logic, recirculation control logic and mode selector control logic. The clock control logic includes a first switch for selecting the repetition rate of bursts of clock pulses which read the analog input information signal into the memory unit of the system and a second switch for selecting the number of clock pulses in the burst. The recirculation control logic includes a switch for obtaining recirculation of the stored information and selecting the number of recirculations between successive read-ins of new analog information. The mode selector control logic determines the mode (read-in or recirculate) of operation of the memory system.

Universal Function Theory and Galois Logic Studies

Abstract: : The report advances work in two areas relevant to logic design in an MSI/LSI technology. First, the theory of universal functions is advanced of the full generality of finite mathematical structures. Second, the theory of Galois logic design is enhanced in various ways. Various Galois lattice-like operations are defined and compared. Next, methods of converting Galois multiplication gates to binary addition gates and to Galois linear gates are described. Finally, techniques are offered using the Galois linear module to reduce hardware at the cost of switching speed.

Analog and computer electronics for scientists

Abstract: ANALOG ELECTRONICS. Circuits and Schematics. Operational Amplifiers 1. Operational Amplifiers 2. Semiconductors. Diodes and Transistors as Circuit Elements. Transducers. Switching Circuits. Power Supplies. DIGITAL ELECTRONICS. Binary Numeration. Binary Logic Gates. Flip--Flops and Registers. Interdomain Converters. COMPUTER ELECTRONICS. The Computer as an Electronic Device. Computer Peripherals. Data Communications. Computer Networks. Construction and Troubleshooting. A Glimpse of the Future. Mathematical Background. Questions and Problems. Appendices. Glossary. Index.

Fault restoration using N-fail-safe logic

Abstract: A new scheme for fault restoration in logic circuits using N-fail-safe logic is proposed. Its failure probability is shown to be significantly less than those of the majority voting scheme and quadded logic, although the cost of realization is comparable to both.

Modular requirements for digital logic simulation at a predefined functional level

Abstract: Simulation of digital logic provides a viable technique for development and diagnosis of digital systems. Simulation models currently employed are discussed with a summary of structure and timing techniques. A methodology for functional simulation in conjunction with gate level simulation is discussed, presenting a representative set of predefined functions, and introducing a measure for predefined function performance. Errors in design detectable at the functional level are catagorized.