Showing papers on "Digital electronics published in 1981"

An Information Theoretic Approach to Digital Fault Testing

Abstract: The concepts of information theory are applied to the problem of testing digital circuits. By analyzing the information throughput of the circuit an expression for the probability of detecting a hardware fault is derived. Examples are given to illustrate an application of the present study in designing efficient pattern generators for testing.

A Voiceband Codec with Digital Filtering

Abstract: Oversampling and digital filtering have been used to design a per-channel voiceband codec with resolution that exceeds the typical transmission system requirement by more than 15 dB. This extended dynamic range will allow for the use of digital processing in the management of signal levels and system characteristics in many telecommunication applications. Digital filtering contained in the codec provides rejection of out-of-band inputs and smoothing of the analog output that is sufficient to eliminate the need for analog filtering in most telephone applications. Some analog filtering may be required only to maintain the expanded dynamic range in cases where there is a danger of large amounts of out-of-band energy on the analog input impairing the dynamic range of the modulator. The encoder portion of the oversampled codec comprises an interpolating modulator that samples at 256 kHz followed by digital filtering that produces a 16-bit PCM code at a sample rate of 8 kHz. In the decoder, digital processing is used to raise the sampling rate to 1 MHz prior to demodulation in a 17-level interpolating demodulator. The circuits in the codec are designed to be suitable for large-scale integration. Component matching tolerances required in the analog circuits are of the order of only ± 1 percent, While the digital circuits can be implemented with fewer than 5000 gates with delays on the order of 0.1 μs. In this paper the response of the codec is described mathematically and the results are confirmed by measurements of experimental breadboard models.

Optical logic gates using liquid crystal light valve: implementation and application example

Abstract: In this paper, we propose a new method of optically implementing digital logic gates capable of performing all logic operations and give the technique for construction of an array of n-bit parallel adders as a typical application circuit. These gates are implemented using a Hughes liquid crystal light valve operated in the parallel off-state configuration. It is found that all possible functions of two binary variables are realizable with these gates, some as bright-true-logic and some as dark-true-logic. Experimental results will be given using the portions of a single liquid crystal light valve demonstrating the feasibility of AND, NOR, XOR, etc. gate arrays. As an example of implementation of combinatorial circuits, a design for an array of binary adders will also be given.

Apparatus for the dynamic in-circuit element-to-element comparison testing of electronic digital circuit elements

Abstract: Apparatus for the dynamic in-circuit testing of digital electronic devices employs a hardware testing circuit that is set by a microcomputer which takes no direct part in the test, so that the test hardware speed is not limited by the computer speed. The apparatus comprises a library of devices equivalent to the devices to be tested, the library including a ROM containing the information regarding the devices needed by the microcomputer for its purpose. An internal interface or router receives signals from the test device that are input signals to its terminals and routes them directly to the corresponding selected device in the library where it becomes an input to that device also. Signals from the test device that are output signals are routed instead to a comparison block where they are compared with the respective output signals from the library reference device. The signals at each corresponding pin of the two devices are compared and upon the presence of a fault the apparatus stops and identifies the pin or pins on which a fault has been detected. An external interface is provided to shift the signal levels as required between the test device and the transistor-transistor logic devices of the apparatus. The signals are sampled during timed periods to account for different propagation times through the apparatus, and different operating speeds of the devices. Provision is made for external or internal clocks, reset and ground connections.

Device for testing digital circuits using built-in logic block observers (BILBO's)

Abstract: A device for testing a digital electronic circuit, having a first BILBO for generating a pseudo-random test pattern, a second BILBO for analyzing a parallel-input signature, a decoder and at least one status indicator for indicating the status of a circuit under test.

Silicon MESFET digital circuit techniques

Abstract: Silicon MESFET circuits of gate-level complexity are described and compared. Circuits using all-depletion devices (AD circuits) are contrasted with circuits using both enhancement and depletion devices (ED circuits). Computer-aided simulations are used to make the comparisons. Circuit techniques that reduce the sensitivity of the circuit to parasitic capacitances are emphasized. The dynamic logic capability of MESFETs and of the interfacing to other logic families is discussed. Verification with experimental data is provided with results from AD designs of ring oscillators, divided-by-two circuits, and drivers.

Electrical testing apparatus and methods

Abstract: A system is disclosed for generating test data for testing logic circuits. It has a store storing a respective Logic List for each of the basic logic circuit types in the form of a list of logic states identifying terminals of the logic circuit to which specified data inputs are to be applied and terminals at which specified data outputs are expected. Another store generates connection information relating to a particular logic circuit under test and specifies any external conditions applied to that circuit by means of its terminals which modify its operation. Means are provided which then modify the logic states of the Logic List in dependence on the connection information, so as to produce a final set of test data which can be used immediately, or subsequently, to carry out the tests on the particular logic circuit.

A switch-level simulation model for integrated logic circuits

Abstract: The switch-level model describes the logical behavior of digital integrated circuits implemented in metal oxide semiconductors (MOS) technology. A network in this model consists of a set of nodes connected by transistor "switches." Many aspects of MOS circuits can be described which cannot be expressed in the Boolean logic gate model, such as bidirectional pass transistors, dynamic storage, and charge sharing. Furthermore, the logic network can be extracted directly from the mask specification of a circuit by a relatively straightforward computer program. Unlike analog circuit models, however, the nodes in a switch-level network assume discrete logic states 0, 1, and X (for unknown), and the transistors assume discrete states "open," "closed," and "unknown." This model can form the basis of a logic simulator for MOS circuits with performance comparable to logic gate simulators. This dissertation presents a rigorous development of the switch-level model and several simulation algorithms.

Digital circuits and microprocessors

Abstract: From the Publisher: This is a pedagogically conceived text in that it enables students to study in one semester what usually takes two,thus teaching every engineer or computer scientist what he or she needs to know about logic design in half a semester. For courses in logic design and microprocessors,digital logic and computer design,and switching theory and logic design.

The Modeling and Synthesis of Bus Systems

Abstract: A bus oriented interconnection of registers and data operators is the dominant mode of design for the data paths of digital systems. A study of ten processor implementations, ranging in size from microprocessors to large mainframes, spanning almost 20 years in the practice of digital design, indicated a strong similarity. From this study bus style primitives and generic bus models were developed. The generic bus models were simplified to match each of the ten processors composing the study. An algorithm for generating a bus style design is presented. The algorithm is used to generate the data paths of the PDP-11/40 resulting in lower cost and shorter delays than the original implementation. Finally, the paper concludes with a discussion of the bus synthesis algorithm's implementation and its role in the CMU functional-to-hardware Design Automation System.

Method of testing a logic system and a logic system for putting the method into practice

Abstract: A method for testing a logic system of the type having points not directly accessible from the exterior, and logic systems including means for carrying out the method. A particular logic state may for test purposes be applied (set) at a particular, normally-inaccessible point in the system; or the logic state at a particular, normally-inaccessible point in the system may be sampled. To accomplish these functions, there are a plurality of flip-flops and associated selective gating circuitry, for example AND-OR select gates, arranged selectively either to connect the flip-flops in series to form a shift register configuration whereby data defining particular logic states to be set, or particular logic states which have been sampled, may be clocked in or clocked out by accessing only the input of the first flip-flop or the output of the last flip-flop; or to connect the inputs and outputs of the various flip-flops to particular points in the system for the purposes of setting and sampling logic states. The logic system may, for example, be either a single integrated circuit chip, or a circuit module having a limited number of external connections.

Automated partitioning of hierarchically specified digital systems

Abstract: This paper describes a heuristic algorithm for automatically partitioning digital systems. High- level information contained within a hierarchical design is used to increase the effectiveness of this algorithm. This algorithm uses a constructive process to build a physical design of a hierarchically specified logic design. An iterative improvement step is then done.

The Analog Behavior of Digital Integrated Circuits

Abstract: The analog behavior of digital VLSI circuits is investigated. A theory based on nonlinear Thevenin equivalent circuits and RC ladder networks is developed. We obtain closed form expressions for the upper and lower bounds on propagation delay through a string of inverters. We generalize this to multiple-input, multiple-output gates and show that the problem of estimating signal propagation delays in VLSI circuits may be reduced to the problem of summing the step responses of a set of linear RC networks. As well as having implications for a computationally efficient timing simulator, the theory begins the formalization of the fundamental properties of digital integrated circuits.

A MOS Modelling Technique for 4-State True-Value Hierarchical Logic Simulation or Karnough Knowledge

Abstract: Modelling strategies and techniques are given for static and dynamic MOS transistors in a 4--state (0/low, 1/high, Z/high-impedance, U/undefined) logic simulator environment. General MOS modelling problems are presented and a set of workable solutions are developed. Experience with these techniques is shown along with examples of NMOS simulation applications. This paper discusses a technique with specific conventions for modelling MOS devices at the "logical transistor" gate level. The technique is not the optimal general solution, but was found to be satisfactory for retrofitting an existing 4--state logic simulator to include MOS capabilities. The technique is not meant to replace analog circuit simulation, but is aimed at increasing the accuracy of MOS logic (gate level) simulations. We begin with a general bus model and extend it to handle transistors, pullups and pulldowns, and dynamic MOS transfer gates. Extensions are shown for a bidirectional transfer gate model that can be connected in any topological configuration.

Logic circuit with a test capability

Abstract: A flip-flop circuit receives a portion of a multiple bit output from a combinational logic circuit to be tested, and feeds back a plurality of bits to comprise a portion of the multiple bit input to the combinational logic circuit. The flip-flop circuit includes a plurality of master and slave flip-flops with the master flip-flops being operable in parallel to receive the output from the combinational logic circuit or in series as a shift register, and the slave flip-flops being operable either in parallel to receive outputs from the master flip-flops or in series as a shift register. The occurrence of a fault in a combinational logic circuit can be determined by examining the contents of either the master or slave flip-flops at a particular clock cycle.

Power supply circuit of intergrated circuit

Abstract: PURPOSE:To obtain a CMOS wherein analog circuit and digital circuit are mounted on a chip and stable amplification is carried out, by separating a circuit for supply power source to a part for analog circuit and a part for digital circuit and power sources are independently supplied to these circuits. CONSTITUTION:Power is supplied to analog circuit cells 2, 3 and digital circuit cell 8 from pads 4-7. Pads 9-21 are provided for input and output. These pads are connected to a lead frame 23 through wiring 24 and then connected to external circuits. When the power supply circuit for analog and digital circuits is divided, a filter is formed between these circuits, preventing input of noise voltage into analog circuit during operation of digital circuit. Moreover, the optimum supply voltage can be set individually and individual control also becomes possible. According to this structure, a COMS device accommodating an amplifier with high amplification factor, digital circuit and analog circuit on the same chip and assuring stable amplification operation can be obtained.

Derivation of universal logic modules, for n ⩾ 3, by algebraic means

Abstract: Universal logic modules (ULMs) are digital circuit configurations which, by appropriate connection to their input terminals, can be made to realise all possible combinational logic functions of a given number of independent binary input variables. The paper describes a method for deriving ULM circuits in general, and in particular considers circuits with three input variables. These are known to need at least five input terminals, and several circuit configurations with this minimum number exist in the literature. The paper discloses five more; four of the five involve negation of the output, but the fifth does not.

Noise Analysis of Soft Errors in Combinational Digital Circuits Via Walsh Transforms

Abstract: The noise produced at the output of combinational logic circuits by individual gate failures is analyzed through the use of Walsh functions. Soft errors are modeled by allowing the output of each gate in a particular realization to fail temporarily, possibly introducing an error in the single binary output. The input variables also are allowed to be stochastically driven. The output probability of error contains the Walsh transform of an extended logic function and the Walsh characteristic functions of the input variables as well as the individual gate failure variables. These results are specialized to the case where the inputs are statistically independent of the soft errors. A discussion of the transform of the extended logic function is included.

An Integrated Computer Aided Design System for Gate Array Masterslices: Part 1. Logic Reorganization System Lores-2

Abstract: The outline and the application results of a computer aided logic design system which combines automatic translation of TTL SSI/MSI logic into gate array logic, human intervention, auxiliary logic simulation, and automatic documentation are described. Automatic translation of logic circuit is done by macro expansion technique coupled with redundant logic reduction procedures.

Digital Circuits with Microprocessor Applications

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Color image pickup unit

Abstract: PURPOSE:To make it possible to prolong memory time, to reduce electric power consumption and to adjust white balance easily and accurately, by storing a digital circuit with the control signal of a gain control circuit for control over the gain of a color signal CONSTITUTION:Red and blue signal systems are provided with gain control circuits 13a and 13b respectively and gains are controlled with the outputs of D/A converters 14a and 14b The outputs of gain control circuits 13a and 13b are compared to the level of a green signal by deciding circuits 15a and 15b to determine the directions of increases or decreases of reversible counting circuits 16a and 16b composed of digital circuits, thereby generating control signals for gain control circuits 13a and 13b

Design of a dynamically programmable logic gate

Abstract: An eight-transistor static logic gate has been designed, which generates the functions OR, NOR, and, nand, xor, and XNOR of two logic variables, under the dynamic control of two programming variables. In addition to its versatility as a building block, the dynamic programmability of the gate makes it a powerful tool for the efficient design of complex digital networks.

Device for testing a digital circuit with test circuits enclosed in this circuit

Abstract: 1. A device for testing a digital electronic circuit by means of test circuits (3, 5) which are incorporated into this circuit, where a first integrated test circuit (3) is provided to generate a pseudorandom test pattern, - where the first integral test circuit (3) is connected to the inputs of the circuit (2) to be tested, - where the first integral test circuit (3) has input signal inputs (Z1A ...Z8A ) and control signal inputs (B1A , B2A ), a number of series connected storage elements (41...48) and means (61...68, 71...78) which serve to adapt the logic level of input signals to the inputs of the storage elements (41...48), which means (61...68, 71...78) connect an output of at least one storage element (41...48) to the input of another storage element (41...48), - where a second integral test circuit (5) is provided to analyse a parallel input word, - where the second integral test circuit (5) is connected to the outputs of the circuit (2) to be tested and has a number of series connected storage elements (141...148) and means (161...168, 171...178) which serve to adapt the input signals for these storage elements (141...148) and which connect the output of at least one storage element (141...148) and the input of a further storage element (141...148), - where a decoder (6) is provided, of which inputs (Q1B ...Q8B ) are connected to outputs of the second integral test circuit (5) in order to receive input signals comprising of a predetermined combination of logic levels in the event that the circuit (2) to be tested is fault-free and which comprise a combination of logic levels which differs from the predetermined combination in the event that the circuit (2) to be tested is faulty, and - where the second integral test circuit (5) has a number of input signal inputs (Z1B ...Z8B ), where a first group of these input signal inputs (Z1B ...Z8B ) is connected via switches (22) to outputs of the circuit (2) to be tested, and a second group of these inputs (Z1B ...Z8B ) is supplied, via switches (22), with input signals which represent a first logic value, e.g. "1", characterised in that - an output of the decoder (6) serves to emit a first output signal in the event that the circuit (2) to be tested is fault-free and to supply a second output signal in the event that the circuit (2) to be tested is faulty, - that at least one status indicator (7 or 8) is provided, which is connected to the output of the decoder (6) in order to indicate the status of the circuit (2) to be tested, - that means (20, 40) are provided which serve to control the first integral test circuit (3) and the decoder (6) in dependence upon a main clock signal (c), - that the control means comprise a control circuit (20) and a clock control circuit (40) which is controlled by a clock control pulse (p) from the control circuit (20), - that the clock control circuit (40) supplies the decoders (6) with an end-of-test signal (w) when a predetermined number of clock pulses of the main clock signal (c; c') have occurred, where the end-of-test signal (w) indicates the end of the testing of the circuit (2) to be tested, - that the control circuit (20) forms a release signal (e) which controls the first integral test circuit (3) and the second integral test circuit (5), where the release signal (e) comprises a sequence of a predetermined number of pulses, - that the control circuit (20) also produces the end-of-test signal (w) at the time of the occurrence of the last pulse of the sequence of a predetermined number of pulses, - that the end-of-test signal (w) is fed to a blocking device (32) in order to emit to the respective status indicator (7; 8) that item of information which is currently present in the decoder (6), - that the first integral test circuit (3) has a plurality of input signal inputs (Z1A ...Z8A ) which are sub-divided into a first group and a second group, - that first input signals, which represent the logic value "0", are fed to this first group of inputs and second input signals, which represent the logic value "1", are fed to this second group of inputs, - that outputs (Q1B ...Q8B ) of the second integral test circuit (5) emit non-inverted output signals, - that each output of a first group of outputs (Q3B , Q8B ) of the second integral test circuit (5) is connected via an individual inverter (24, 25) to the decoder (6), where this first group of outputs (Q3B , Q8B ) emits output signals having a first logic level in the event that the circuit (2) to be tested is fault-free and - that the outputs of the inverters (24, 25) and a second group of outputs (Q1B , Q2B , Q4B , Q5B , Q6B and Q7B ) of the second integral test circuit (5) are connected to corresponding inputs of the decoder (6), where each output of the second group has a second logic level in the event that the test circuit (2) to be tested is fault-free.

Circuit for generating test signals for in-circuit digital testing

Abstract: A circuit for use with a central processor for the in-circuit testing of the electrical properties of components interconnected at electrical nodes in a circuit under test is disclosed. The nodal test signals have first, second, and disconnect logic states. A test vector processor responds to the central processor to control the generation of the nodal test signals during a test cycle. A plurality of digital test signal means responsive to the vector processor are also provided. Each test means includes a circuit means for storing test signal generating data, and responsive to the stored data, controls the generation of the logic state of a nodal test signal where the logic state of the test signal is controlled to (1) keep the same logic state as the previous logic state, (2) toggle to the opposite state as the previous logic state, or (3) assume either a logic zero or a logic one state regardless of the previous logic state.

Gallium arsenide large scale integrated circuits

Abstract: Large scale digital integrated circuits containing over 6000 active devices (1 μm MESFETs and Schottky diodes) have recently been achieved in GaAs Schottky Diode FET Logic. The planar, ion implanted process used to fabricate these circuits results in very uniform device properties because of the excellent control of critical device interfaces. The present status of LSI GaAs ICs is reviewed, including a description of the performance of an 8×8 bit multiplier LSI circuit. VLSI circuit prospects and the applicability of new high speed GaAs active devices for VLSI application in GaAs are considered.

Apparatus for the dynamic in-circuit testing of electronic digital circuit elements

Abstract: Apparatus for the dynamic in-circuit testing of digital electronic devices employs a hardware testing circuit that is set by a microcomputer (26) which takes no direct part in the test, so that the test hardware speed is not limited by the computer speed. The apparatus comprises a library (20) of devices corresponding to the devices to be tested, the library (20) including a ROM containing the information regarding the devices needed by the microcomputer (26) for its purpose. An internal interface or router receives signals from the test device that are input signals to its terminals and routes them directly to the corresponding selected device in the library (20) where it becomes an input to that device also. Signals from the test device that are output signals are routed instead to a comparison block (18) where they are compared with the respective output signals from the library (20) reference device. The signals at each corresponding pin of the two devices are compared and upon the presence of a fault the apparatus stops and identifies the pin or pins on which a fault has been detected. An external interface is provided to shift the signal levels as required between the test device and the TTL logic devices of the apparatus. The signals are sampled during timed periods to account for different propagation times through the apparatus, and different operating speeds of the devices. Provision is made for external or internal clocks, reset and ground connections.

Expected value analysis of combinational logic networks

Abstract: The results of an investigation into probabilistic analysis of combinational digital networks are reported herein. Basic gates as well as larger functional building blocks are assigned probability density functions in place of fixed input-output propagation delays. Signal lines interconnecting logic device models carry not I or 0 (binary) values, but rather continuous waveforms representing the expected values of these binary signals. Probabilistic models of the basic AND, OR, NOT, etc., gates are presented, as are methods for handling signal dependencies due to reconvergent fanout. Application of the models to reliability analysis is discussed.