Showing papers on "Digital electronics published in 1986"

Semi-conductor integrated circuits/systems

Abstract: Configurable semiconductor integrated circuits as-made each have a plurality of logic circuits formed at discrete sites. For each logic circuit, direct selectably conducting/non-conducting connection paths extend from its output to input of a first set of other logic circuits and to its inputs from outputs of a second set of other logic circuits. All of the sets for all of the logic circuits are each different. Other direct connection paths are selectably connectable to inputs and outputs of the logic circuits. Selection can be irreversible or reversible and involves coincident signal addressing of the sites and coded configuring of the paths at that site. Reversible selection can be via field effect transistors or bipolar transistors and can be at or near normal logic signal levels and speeds. Versatile configurable input/output arrangements are described also reconfigurable data processing systems using the reversible transistor provisions.

SOCRATES: A System for Automatically Synthesizing and Optimizing Combinational Logic

Abstract: This paper presents SOCRATES, a system of programs which synthesize and optimize combinational logic circuits from boolean equations. SOCRATES optimizes logic using boolean and algebraic minimization techniques, and it optimizes circuits derived from this logic in a user defined technology with a rule based expert system. This paper discusses the goals of logic synthesis and the capabilities needed in a tool to meet these goals. SOCRATES's capabilities are then presented and demonstrated with experiments run on circuits from the 1986 Design Automation Conference synthesis benchmark set.

Macromodeling and Optimization of Digital MOS VLSI Circuits

Abstract: Power consumption and signal delay are crucial to the design of high-performance VLSI circuits. This paper presents CAD tools for modeling and optimizing digital MOS designs. The tools determine the transistor sizes that minimize circuit power consumption subject to constraints on signal path delays. Computational efficiency is obtained through macromodeling techniques and a specialized optimization algorithm. The macromodels are based on device equations, and encapsulate logic gate behavior in a set of simple yet accurate formulas. The optimization algorithm exploits properties of the digital MOS domain to convert the primal optimization problem into a dual form which is much easier to solve. The result is a pair of CAD tools that can optimize a circuit in roughly the amount of time needed to perform a transistor-level simulation of the circuit.

Optical Clock Distribution To Silicon Chips

Abstract: Timing constraints for state-of-the-art very large scale integrated circuits (VLSI) in silicon are rapidly approaching communication limits available with layered two-dimensional metal and polysilicon wiring approaches. For such communication-limited systems, reliable clock distribution is a key concern. The range of finite differences in signal delays over clock wires of various lengths for large chips creates a timing skew that is significant when compared to the switching time of transistors in the circuit. The high bandwidth and three-dimensionality of imaging optical systems suggest that optical clock distribution systems have the potential to overcome the timing barriers presented by planar wiring. Clock signals can be holographically mapped to detector sites within small functional cells on a chip surface. Within each functional cell, the clock is distributed with negligible delays via surface wires, reducing skew effects to the variation in reaction times of the photodetectors on the chip. This paper includes the presentation of an optical clock distribution system assuming holographic mapping of beams from an off-chip optical source. Computer simulations of the electronic response of optical clock detection circuits in standard 4 µm CMOS technology have been performed.

Design-performance trade-offs in CMOS-domino logic

Abstract: The authors present a study of the charge-sharing problem and its effect on the performance of CMOS-domino logic. Several solutions to the charge-sharing problem are examined, and the results are verified by simulation. Thus, the charge-sharing problem in CMOS-domino logic was identified and alternate approaches were evaluated.

Electronic Logic Systems

Abstract: Part 1 Principles of logic systems: combinational logic logic and memory devices combinational logic at different levels of integration synchronous sequential circuits asynchronous sequential circuits arithmetic logic circuits. Part 2 Advanced logic systems: combinational logic techniques partitioning of sequential circuits partition-based design for synchronous sequential circuits partition-based design for asynchronous sequential circuits hybrid design techniques for sequential circuits CAD of logic circuits.

Digital Simulation with Multiple Logic Values

Abstract: Multiple-valued logics have long been used, often in intuitive fashion, for simulating transients, errors, unknown states, variable-strength signals, etc., in binary digital circuits. This paper presents a rigorous algebraic method for analyzing such logics, and for systematically constructing new ones. Starting with a basis such as 2-valued Boolean algebra, new algebras suitable for a broad range of practical simulation tasks are obtained systematically via a small set of expansion operations. This approach is applied in detail to the construction of families of simulation algebras for gate-level logic circuits; switch-level simulation is also considered. It is concluded that current simulation programs frequently lack essential logic values, and occasionally have superfluous ones. Some major discrepancies in the number of distinct logic values claimed by commercial simulators are also explained.

Sample-set differential logic (SSDL) for complex high-speed VLSI

Abstract: An improved CMOS logic circuitusing a differential cascode tree with sample and set phases of operation is presented. The sample-set differential logic (SSDL) circuit allows the use of several transistors in series in the cascode tree without significant speed degradation. Also, the signals arriving at the input require only a short valid time, which allows long interconnect delays. This improved logic circuits is compared with two other common CMOS logic circuits in a simulated design example.

Soft-error filtering: A solution to the reliability problem of future VLSI digital circuits

Abstract: As the semiconductor industry continues to scale down the feature sizes in VLSI digital circuits, soft errors will eventually limit the reliability of these circuits. An important source of these errors will be the products of radioactive decay. It is proposed to combat these transient errors by a new technique called soft-error filtering (SEF). This is based on filtering the input to every latch in the VLSI circuit, thereby preventing these transients, generated by alpha particle hits in the combinational section, from being latched in the corresponding registers. Several approaches to the problem of designing filtering latches are compared. This comparison demonstrates the superiority of a double-filter realization. The design for a CMOS implementation of the double-filter latch is presented. Not only is the design simple and efficient, but it can be expected to be tolerant to process variations. A comparison of SEF with conventional techniques for dealing with soft errors shows the former to be generally much more attractive, from the point of view of both area and time overhead.

CMOS/bipolar circuits for 60-MHz digital processing

Abstract: High-performance bipolar/CMOS (Hi-BiCMOS) technology, in which a bipolar transistor of 4-GHz cutoff frequency is combined with standard CMOS devices on the same chip, has been applied to a processor. The design strategy was to provide high integration density using the CMOS circuit and accelerate the critical paths using the Hi-BiCMOS circuits. Hi-BiCMOS circuits with low-voltage swing have been developed and applied to a 32-bit arithmetic logic unit and a 128-kb ROM with bipolar drivers to drive a heavy load capacitance. A 17-ns 32-bit carry propagation delay time and a 17-ns ROM access cycle time have been achieved using 2-/spl mu/m Hi-BiCMOS technology. A minicomputer CPU with a 60-MHz machine cycle can be implemented with these circuits.

Multiple-valued threshold logic: its status and its realization

Abstract: Multiple-valued logic, in which the number of discrete logic levels is not confined to two, as is the case with all present-day digital systems, has many theoretical advantages. Multiple-valued threshold logic has particular attractions but, as with all forms of logic with more than two logic levels, is presently constrained by the lack of good devices for system realization. In this paper we introduce the theoretical attractions of multiple-valued digital systems and look toward optoelectronics for more realistic devices in the future.

Enhanced CMOS for analog-digital power IC applications

Abstract: Elementary process additions to 2-3-µm polygate CMOS provide enhanced high-voltage MOSFET's and broadband complimentary bipolars. This allows monolithic integration of a modern logic family and quality analog function with high-voltage high-current buffers and drivers. The technology is suitable for data conversion, telecommunication, analog switch, and industrial IC applications where low-voltage digital and analog control circuitry must be interfaced to high-voltage high-current outputs.

Multimemory block structure for implementing a digital adaptive filter using distributed arithmetic

Abstract: A new structure of adaptive transversal filters with a large number of taps is described. It is based on the use of the distributed-arithmetic technique without any multiplier in the realisation of the filter function. In this structure, the N filter taps are divided into M blocks, each with R taps. These M blocks operate simultaneously and thus achieve a high-speed signal processing capability. This type of adaptive filter can easily be implemented by using microprocessor or transistor-transistor logic integrated circuits. A simplified hardware prototype module suitable for 8- and 16-point transversal adaptive filters, using microprocessor and simple peripheral interface circuitry, is presented. Results from this prototype demonstrate the basic feasibility of this structure for implementing digital adaptive filters with a large number of taps.

Functional Test Generation for Digital Circuits Described Using Binary Decision Diagrams

Abstract: This correspondence presents a test generation methodology for VLSI circuits described at the functional level. A VLSI circuit is modeled as a network of functional modules such as registers, adders, RAM's, and MUX's. The functions of the individual modules are described using binary decision diagrams. A functional fault model is developed independent of the implementation details of the circuit. A generalized D algorithm is proposed for generating tests to detect functional as well as gate-level faults. Algorithms which perform fault excitation, implication, D propagation, and line justification on the functional modules are also described.

Latched domino CMOS logic

Abstract: A new gate configuration, the latched domino (Ldomino) CMOS gate, is presented. It can be used to alleviate the inversion problem inherent in domino CMOS, while improving speed and reducing layout area. Ldomino logic can serve as an efficient interface stage between blocks of static and domino or differential-cascode voltage-switch logic. The function of interfacing single-ended logic signals to differential domino-compatible logic signals is combined with the capability of efficient implementation of complex logic functions, thereby improving the logic flexibility of domino logic. A simple 4-bit ALU is used as an illustrative example of the application of Ldomino logic.

Handbook of Modern Electronics and Electrical Engineering

Abstract: MATHEMATICS: Units and Constants Formulas Used in Engineering PROPERTIES OF MATERIALS: Insulating and Dielectric Materials COMPONENTS: Active Lumped Circuit Elements Microwave Devices PASSIVE CIRCUITS: Passive Filters Computer-Aided Circuit Analysis Active Circuits DIGITAL CIRCUITS: Flip-Flops and Registers SYSTEMS ENGINEERING, AUTOMATIC CONTROL AND MEASUREMENTS: Automatic Control Robotics MEDICAL APPLICATIONS OF ELECTRONICS: Introduction to Human Physiology Patient Monitoring SOUND AND VIDEO RECORDING AND REPRODUCTION: Audio Recording and Playback Communications Techniques RANGING, NAVIGATION AND LANDING SYSTEMS: Radar COMPUTERS: Data Structures Memory Systems Computers Communication Networks ENERGY ENGINEERING: Energy Management Index.

A Fast-Timing Simulator for Digital MOS Circuits

Abstract: An efficient and accurate algorithm has been developed for predicting the timing waveforms of general MOS transistor circuits. The algorithm uses a switch-level simulation technique to determine the steady-state conditions, a forward prediction method to predict the transient time between two adjacent voltage levels, a simplified timing simulation technique to correct this delay, and novel approaches for controlling the voltage step automatically. The simulation is further speeded up by the use of a table lookup model to calculate the transistor current and macromodels to evaluate certain circuit structures. This algorithm has been implemented as a new simulation mode, called fast timing, in the MOTIS3 multilevel mixed-mode simulator. Many production chips have been verified, and the results show that the fast-timing simulation can be three orders of magnitude faster than a conventional circuit analysis program such as SPICE, one order of magnitude faster than the MOTIS3 timing simulation, and only five times slower than the MOTIS3 unit-delay, switch-level evaluator. The delay accuracy of the new simulator is within 5 percent of the timing simulation.

Modern Digital Electronics

Abstract: Part of the McGraw-Hill Core Concepts Series, Modern Digital Electronics is an ideal textbook for a course on digital electronics at the undergraduate level. The text introduces digital systems and techniques through a bottom-up approach that allows users to start out with the basics of integrated circuits/circuit design and delve into topics such as digital design, flip flops, A/D and D/A. The book then moves on to explore elements of complex digital circuits with material like FPGAs, PLDs, PLAs, and more. Rich pedagogical features include review questions with answers, a glossary of key terms, a large number of solved examples, and numerous practice problems. This is a concise, less expensive alternative to other digital logic designs. This series is edited by Dick Dorf. Table of contents 1 Fundamental Concepts2 Number Systems and Codes3 Semiconductor Devices—Switching Mode Operation4 Digital Logic Families5 Combinatorial Logic Design6 Combinational Logic Design Using MSI Circuits7 FLIP-FLOPs8 Sequential Logic Design9 Timing Circuits10 A/D and D/A Converters11 Semiconductor Memories12 Programmable Logic Devices13 Fundamentals of Microprocessors14 Computer-Aided Design of Digital Systems

Logic Synthesis and Optimization Benchmarks for the 1986 Design Automation Conference

Abstract: In order to compare logic synthesis and optimization systems, a set of benchmarks has been submitted to a number of authors. The results obtained are reported in the present proceedings. This short paper introduces the benchmarks as well as a set of criteria to measure the quality of logic synthesis systems.

Method of and apparatus for fault detection in digital circuits by comparison of test signals applied to a test circuit and a faultless reference circuit

Abstract: A fault detection system for electronic circuits is disclosed which comprises a detection circuit in which the crosscorrelation values between the test signal sequence, input to a circuit to be tested, and the output signal sequence from it, with no delay and with delays made in steps to a predetermined time interveral either in the test input signal or in the output sequence, are counted, a reference circuit in which the crosscorrelation values between the test signal sequence input to a faultless reference circuit and the output signal sequence from it, are counted, and a comparator for comparing the crosscorrelation values from both the detection and reference circuit In one preferred embodiment, one or more of the conventional data compression methods selected from the group of the one's counting, transistion counting, auto-correlation, and C R C methods are incorporated for operation in conjunction with the system

Modeling MOS VLSI circuits for transient analysis

Abstract: Modeling plays a significant role in the efficient simulation of VLSI circuits. By simplifying the models used to analyze these circuits, it is possible to perform transient analyses with reasonable accuracy at speeds of one or two orders of magnitude faster than in conventional circuit simulation programs. The author discusses the models that are used in the second-generation MOTIS timing simulator. The methods used have been applied to a wide variety of MOS digital integrated circuits. All MOS transistors are modeled as voltage-controlled current sources using multidimensional tables. The actual currents are computed by approximation using variation-diminishing tensor splines. Nonlinear device capacitances in the circuit are approximated using linear models which are derived from experimental simulations using a circuit simulator. At the subcircuit level, special structures in the circuit are identified automatically by a preprocessor and are modeled using macro-models. Driver-load MOS transistor gates and bootstrapped circuits are examples of these structures. Their modeling is achieved by an experimental process before implementation in the preprocessor. The simplifications in the device and circuit models presented here have provided a significant improvement in the speed of transient analysis for large MOS digital circuits with relatively little loss in accuracy. This has resulted in a viable design verification environment using MOTIS.

A Logic Verifier Based on Boolean Comparison

Abstract: This paper proposes a logic VERIFIER, which verifies the correctness of the gate-level design by comparing it with the behavioral description. An improved Boolean comparison technique, which assures the absence of errors without designer's assist, is proposed. The partitioning and the minimization techniques are effective to reduce the storage required, and indispensable to verify practical sized circuits. If the design is judged incorrect, the system analyzes the result and show the area containing errors. Experimental results have proved that the VERIFIER can detect design errors completely, and indicate them to the designers in comprehensible form.

FAUST: An MOS Fault Simulator with Timing Information

Abstract: This paper describes FAUST, an MOS fault simulator with timing information. FAUST simulates the effects of realistic physical failures on MOS circuits and uses a static concurrent fault-simulation technique to evaluate the fault-free circuit and all the faulty circuits in one pass. FAUST produces voltage waveforms as well as logic tables with delay information for the fault-free circuit and for each of the faulty circuits.

Micro-stepping translator controller

Abstract: A micro-stepping translator controller for supplying current to a stepping motor having a plurality of windings comprises a power supply for supplying current to all windings and electronic switches for gating current to all windings. Logic means receive inputs comprising a clock input having a frequency being indicative of the micro-stepping rate and a multiplexing pulse. The logic means having digital circuits for outputting over a data bus signals indicative of two quadrants of a stepped periodic function. The signals correspond to different phases of the stepped periodic function during different multiplexing intervals. The logic means has digital circuits for sequentially outputting signals indicative of one of the four quadrants. A digital-to-analog converter is connected to the output data bus for producing an analog signal. Multiplexing and inverting means select and during some multiplexing intervals invert the output of the digital-to-analog converter in response to the multiplexing pulse and a signal indicative of quadrant, to produce at least two interleaved stepped periodic signals. An output circuit including said electronic switches, in response to said at least two interleaved stepped periodic signals, gate the electronic switches on and off during one-half of the cycle of one of said stepped periodic functions.

Gate propagation delay and logic timing of GaAs integrated circuits measured by electro-optic sampling

Abstract: We report techniques for measuring internal switching delays of GaAs digital integrated circuits by electro-optic sampling. Circuit propagation delays of 15 ps are measured. A new phase modulation technique which allows testing of sequential logic is demonstrated with the measurement of a 2·7 GHz 8-phase clock generator.

A CMOS VLSI chip for filtering of TV pictures in two dimensions

Abstract: Low-cost digital transmission of color TV signals over the channels of a future broad-band network (Integrated Services Digital Network, or ISDN) requires data reduction by digital low-pass filters. Low-pass filtering of a TV picture amounts to process pixels which are adjacent in either the horizontal or vertical direction. For this purpose, the pixels must be stored in a delay unit. A VLSI chip with a delay unit is reported that is based on a resettable first-in-first-out (FIFO) memory and a pipelined arithmetic unit. The FIFO concept starts from a three-transistor cell array which is accessed by a pointer and customized to a FIFO memory by suitable second-layer metal wiring. Rather than cascade registers, the FIFO memory can be adapted to different standards by the reset signal for the pointer. The approach results in a regular compact design (80-kbit transistors, 31 mm/SUP 2/). An experimental chip fabricated with 1.5-/spl mu/m CMOS technology operates up to 22 MHz (typical values). A data stream of 22/spl times/32 Mb/s is exchanged between the memory and the arithmetic basic unit.

Design of a reliable and self-testing VLSI datapath using residue coding techniques

Abstract: The testing of VLSI circuits is becoming progressively more difficult as device densities increase. This has brought about several proposals for designing VLSI circuits with testability built in. A method is presented in the paper for the design of easily testable VLSI circuits with a view to producing fault tolerant systems. A microprocessor datapath is used to illustrate the technique. The method used for checking the VLSI devices is an error detecting code, in this case a residue code. Residue codes offer several advantages over linear block codes for providing testability in a wide range of VLSI circuits. A detailed evaluation of the increase in chip area required to produce a self testing chip is also given in the paper.