Showing papers on "Digital electronics published in 1988"

Picosecond optical sampling of GaAs integrated circuits

Abstract: Direct electrooptic sampling is a noncontact optical-probing technique for measuring with picosecond time resolution the voltage waveforms at internal nodes within GaAs integrated circuits. The factors contributing to system bandwidth, sensitivity, spatial resolution, and circuit perturbation are discussed, as are the circuit requirements for realistic testing of analog and digital devices. Measurements of high-speed GaAs integrated circuits are presented, including time-domain waveform and timing measurements of digital and analog circuits and frequency-domain transfer function measurements of microwave circuits and transmission structures. >

DELIGHT.SPICE: an optimization-based system for the design of integrated circuits

Abstract: DELIGHT.SPICE is the union of the DELIGHT interactive optimization-based computer-aided-design system and the SPICE circuit analysis program. With the DELIGHT.SPICE tool, circuit designers can take advantage of recent powerful optimization algorithms and a methodology that emphasizes designer intuition and man-machine interaction. Designer and computer are complementary in adjusting parameters of electronic circuits automatically to improve their performance criteria and to study complex tradeoffs between multiple competing objectives, while simultaneously satisfying multiple-constraint specifications. The optimization runs much more efficiently than previously because the SPICE program used has been enhanced to perform DC, AC, and transient sensitivity computation. Industrial analog and digital circuits have been redesigned using this tool, yielding substantial improvement in circuit performance. >

Evaluation and improvement of Boolean comparison method based on binary decision diagrams

Abstract: R.E. Bryant proposed a method to handle logic expressions (IEEE Trans. Comp., vol.25, no.8, p.667-91, 1986) which is based on binary decision diagrams (BDD) with restriction; variable ordering ix fixed throughout a diagram. The method is more efficient than other methods proposed so far and depends heavily on variable ordering. A simple but powerful algorithm for variable ordering is developed. The algorithm tries to find a variable ordering which minimizes the number of crosspoints of nets when the circuit diagram is drawn. This is applied to the Boolean comparison of ISCAS benchmark circuits for test pattern generation. The results show that binary decision diagrams (BDD) with the proposed ordering method can verify almost all benchmark circuits in less than several central processor unit (CPU) minutes, which is one hundred times (or more) faster than times reported in the literature. Some techniques for circuit evaluation ordering are also mentioned. >

A multiple valued logic: a tutorial and appreciation

Abstract: This tutorial places the developments and potential of multiple-valued signals and logic in the relevant context of binary and two-valued signals It covers: the role of multivalued logic (MVL) in the binary world; multivalued representation; binary-related radices; multivalued functions; storage techniques in MVL; and implementation issues An overview of applications is included >

Static timing analysis of semiconductor digital circuits

Abstract: The time verification scheme of the present invention operates without input stimulus to calculate delays along circuit paths including logic elements or cells from initial input to final output, or over sub-circuit paths, of a proposed logic design. The delay calculations include cell-dependent, and layout-dependent, and environmental-dependent factors to account for response delays on rising and falling signal; capacitance loading, temperature-dependency and voltage-dependency of a proposed logic design to provide output histograms and reports of information about overall performance, and timing violations of the proposed logic design with respect to operating parameters that can be selectively adjusted for manufacturing variations.

A new interface specification methodology and its application to transducer synthesis

Abstract: In this dissertation, I present a new methodology for the abstract specification of digital circuit interfaces. An interface is the collection of signal wires that cross a circuit boundary and the constraints on the events on those wires. The specification methodology is based on a formalization of the timing diagrams commonly used by digital circuit designers. This mostly graphic method is not only familiar to its intended users but is also concise in its description. An interactive editor, called Waves, has been implemented to support this methodology and used to describe a wide range of circuit interfaces ranging from static memories, to microprocessors, to system busses. Interface specification has a wide range of uses during the design and evaluation of a circuit. Waves diagrams and the constraints they capture form the basis for an entire new set of CAD tools that reason about interface design, synthesis, evaluation, and testing. One of these applications, the automatic synthesis of interface transducers, is highlighted in this dissertation. An interface transducer is the collection of logic circuitry that connects two compatible circuit interfaces. In general, it includes both synchronous and asynchronous components and must satisfy the timing constraints of both interfaces. Interface transducers are required whenever a custom chip is integrated into a computer system or in general, whenever two circuit blocks need to be connected. Their automatic design can greatly reduce the time required to assemble systems or integrate new components into existing systems. Janus uses a novel approach, based on a small set of templates, to synthesize mixed asynchronous and synchronous control logic. The synthesis algorithm, called Suture, first constructs a skeletal circuit and then locally modifies the design to meet interface timing constraints and eliminate internal race conditions. Optimizations of the resulting sequential logic yield transducers that are comparable in both size and performance to those generated by experienced designers. Three practical examples are used to demonstrate this result.

Computer Engineering: Hardware Design

Abstract: PART I. 1. Binary Numbers and Codes. 2. Digital Circuits. 3. Combinational Systems. 4. Sequential Logic. PART II. 5. Registers and Counters. 6. Memory and Programmable Logic. 7. Register Transfer and Computer Operations. 8. Control Logic Design. PART III. 9. Computer Instructions and Addressing Modes. 10. Design of a Central Processing Unit (CPU). 11. Input-Output and Communication. 12. Memory Management. Index.

On path selection in combinational logic circuits

Abstract: The authors have developed a polynomial-time algorithm to find a minimum cardinality path set that can be used to verify the correct operation of a digital circuit. Although they have assumed that the circuit under consideration is a combinational logic circuit constructed from AND, OR, NAND, NOR, and NOT gates, circuits containing other types of gates can be accommodated by using an appropriate circuit model for such gates. The algorithms are also directly applicable to sequential circuits that use the so-called scan design, since in such circuits it is only necessary to test the combinational circuit embedded between latches. >

Analysis and characterization of BiCMOS for high-speed digital logic

Abstract: A combined bipolar and CMOS (BiCMOS) logic gate, capable of driving large capacitive loads at high speed, is analyzed and characterized. A simple analytical model which accurately predicts the transient response of the BiCMOS gate is described. At moderate and large loads, saturation of the bipolar transistors due to collector resistance can dominate the transient response. Device scaling issues are discussed for minimizing gate delay at various loading conditions. >

Implementation of iterative networks with CMOS differential logic

Abstract: An improved differential CMOS logic family called enabled/disabled CMOS differential logic (ECDL) is presented. An extension to this logic technique which enables the implementation of iterative network arrays is also presented. Two simple logic functions, a Gray-to-binary decoder and an XOR cell, are implemented to demonstrate this methodology. >

A New Interface Specification Methodology and

Abstract: In this dissertation, I present a new methodology for the abstract specification of digital circuit interfaces. An interface is the collection of signal wires that cross a circuit boundary and the constraints on the events on those wires. The specification methodology is based on a formalization of the timing diagrams commonly used by digital circuit designers. This mostly graphical method is not only familiar to its intended users but is also concise in its description. An interactive editor, called Waves, has been implemented to support this methodology and used to describe a wide range of circuit interfaces ranging from static memories, to microprocessors, to system busses. Interface specification has a wide range of uses during the design and evaluation of a circuit. Waves diagrams and the constraints they capture form the basis for an entire new set of CAD tools that reason about interface design, synthesis, evaluation, and testing. One of these applications, the automatic synthesis of interface transducers, is highlighted in this dissertation. An interface transducer is the collection of logic circuitry that connects two compatible circuit interfaces. In general, it includes both synchronous and asynchronous components and must satisfy the timing constraints of both interfaces. Interface transducers are required whenever a custom chip is integrated into a computer system or in general, whenever two circuit blocks need to be connected. Their automatic design can greatly reduce the time required to assemble systems or integrate new components into existing systems. Janus uses a novel approach, based on a small set of templates, to synthesize mixed asynchronous and synchronous control logic. The synthesis algorithm, called Suture, first constructs a skeletal circuit and then locally modifies the design to meet interface timing constraints and eliminate internal race conditions. Optimizations of the resulting sequential logic yield transducers that are compatible in both size and performance to those generated by experienced designers. Three practical examples are used to demonstrate this result.

High-level synthesis of digital circuits using global scheduling and binding algorithms

Abstract: The need to rapidly produce designs of digital integrated circuits has motivated the development of high-level synthesis tools that automatically generate a design of a digital system from an abstract specification of its behavior. This dissertation describes a multi-paradigm implementation of a high-level synthesis tool that features: (1) A new global force-directed scheduling algorithm that attempts to balance the distribution of operations that make use of the same hardware resources; therefore minimizing functional unit, register and interconnection costs. (2) A rule-based expert allocater that performs a global analysis of the control and data flow graph and uses heuristic rules to preselect hardware modules based on a speed constraint. (3) A stepwise refinement approach to scheduling and allocation where preliminary allocation information is used to guide and optimize the scheduling process. (4) Data path synthesis algorithms that attempt to minimize interconnect at all stages of the synthesis process.

On the design of robust multiple fault testable CMOS combinational logic circuits

Abstract: Tests that detect modeled faults independent of the delays in the circuit under test are called robust tests. An integrated approach to the design of combinational logic circuits in which all single stuck-open faults and path delay faults are detectable by robust tests was presented by the authors earlier. It is shown that the earlier design actually results in circuits in which all multiple stuck-at and stuck-open and multipath delay faults are robustly testable. The tests to detect such faults are presented. >

Implementing neural nets with programmable logic

Abstract: Networks of Boolean programmable logic modules are presented as one purely digital class of artificial neural nets. The approach contrasts with the continuous analog framework usually suggested. Programmable logic networks are capable of handling many neural net applications. They avoid some of the limitations of threshold logic networks and present distinct opportunities. The network nodes are called dynamically programmable logic modules. They can be implemented with digitally controlled demultiplexers. Each node performs a Boolean function of its inputs which can be dynamically assigned. The overall network is therefore a combinational circuit and its outputs are Boolean global functions of the network's input variables. The approach offers definite advantages for VLSI implementation, namely, a regular architecture with limited connectivity, simplicity of the control machinery, natural modularity, and the support of a mature technology. >

DCIATP-an iterative analog circuit test generation program for generating DC single pattern tests

Abstract: An algorithm is proposed for automatic test input generation for nonlinear analog circuits and digital circuits with analog behavior under fault. The algorithm uses high-level reasoning with simple iteration to find inputs which will detect resistive shorts and opens that cause DC errors. A simple version of the algorithm, for the time-domain case, has been implemented. Current work includes incorporating the heuristics into the path-generating algorithm, creating tests for larger circuits, extending the fault model to a parameter change in branches other than resistors (e.g. a beta change in a transistor), creating sensitivity metrics for the frequency domain and developing a transient error solution. >

Multiple-valued logic and optimization of programmable logic arrays

Abstract: Shows a method of designing programmable logic arrays (PLAs) using multiple-valued input, two-valued output functions (MVITVOFs). A MVITVOF is an extension of the two-valued logic function. An expression for a MVITVOF directly represents a multiple-output PLA with decoders. Each product of the expression corresponds to each column of the PLA, so the number of products; in the expression equals the number of columns of the PLA. The array size of the PLA is proportional to the number of products; the PLA can thus be minimized by minimizing the expression. >

Synthesis and optimization procedures for fully and easily testable sequential machines

Abstract: A synthesis procedure is described that produces an optimized fully and easily testable logic implementation of a sequential machine from a state transition graph description of the machine. This logic-level implementation is guaranteed to be testable for all single stuck-at faults in the combinational logic. No access to the memory elements is required. The test sequences for these faults can be obtained using combinational test generation techniques alone. It is shown that an intimate relationship exists between state assignment and the testability of a sequential machine. A technique is also presented of don't-care minimization and added observability which ensures fully testable machines. >

Testing digital circuits

Abstract: To test a digital data storage circuit which includes two latch elements (5, 10) each formed by two complementary transistor inverter circuits (S1 S2, S3 S4) connected in a positive feedback arrangement and in which the output current capability of the second inverter circuit is restricted to enable the latch element to change state in response to input signals applied to it, a transistor (T3) is blocked (6) and the first latch element (5) is connected in a two elements per bit shift register configuration with the second latch element (10) by series connected transistors (T4, T5) controlled by antiphase square waves (T3T, H1T). During normal operation asynchronous SET and CLEAR signals are used to control three transistors (T1, T2, T6) whereby to be able to apply (via T3) one of two voltage levels to the first latch (5), one of the shift register transistors (T4) being closed. Each latch (5, 10) may be as shown in Fig 2, the transistors being of differing size, as illustrated. … …

Life after the schematic: the impact of circuit operation on the physical realization of electronic power supplies

Abstract: The impact of the nonlinear analog operation of power electronic circuits on the physical realization process is considered. Portions of the physical realization process of a switched-mode power supply are compared with those of a digital circuit board assembly of exactly the same size and power dissipation. This comparison serves as an illustrative example of how differences in circuit operation prevent power supply engineers from using many of the design methodologies that are so effective in digital applications. >

Characterization of parallelism and deadlocks in distributed digital logic simulation. Draft report

Abstract: This paper explores the suitability of the Chandy-Misra algorithm for digital logic simulation. Four realistic circuits are used as benchmarks for the analysis, with one of them being the vector-unit controller for the Titan supercomputer from Ardent. The results show that the average number of logic elements available for concurrent execution ranges from 6.2 to 92 for the four circuits, with an overall average of 50. Although this is twice as much parallelism as that obtained by traditional event-driven algorithms, it is still felt too low. One major factor limiting concurrency is the large number of global synchronization points - deadlocks in the Chandy-Misra terminology - that occur during execution. Towards the goal of reducing the number of deadlocks, the paper presents a classification of the types of deadlocks that occur during digital logic simulation. Four different types are identified and described both intuitively in terms of circuit structure and formally with equations. Using domain specific knowledge, the paper proposes methods for reducing these deadlock occurrences. For one of the benchmark circuits, the use of the proposed techniques eliminated all deadlocks and increased the average parallelism from 40 to 160. We believe that the use of such domain knowledge willmore » make the Chandy-Misra algorithm significantly more effective than it would be in its generic form. (jhd)« less

Automatic test generation using neural networks

Abstract: An automatic test pattern generation (ATPG) methodology that has the potential to exploit fine-grain parallel computing and relaxation techniques is described. The approach is radically different from the conventional methods used to generate tests for circuits from their gate-level descriptions. A digital circuit is represented as a bidirectional network of neurons. The circuit function is coded in the firing thresholds of neurons and the weights of interconnection links. This neural network is suitably reconfigured for solving the ATPG problem. A fault is injected into the neural network and an energy function is constructed with global minima at test vectors. Global minima are determined by a probabilistic relaxation technique augmented by a directed search. Preliminary results on combinational circuits confirm the feasibility of the technique. >

Optimal logic synthesis and testability: two faces of the same coin

Abstract: The relationships between test generation and logic minimization are described. An overview of the state of the art in combinational and sequential logic synthesis is provided. Combinational logic synthesis algorithms which can ensure irredundant and fully testable combinational circuits are reviewed. Test vectors which detect all single stuck-at faults in the combination logic can be obtained as a by-product of the logic minimization step. Equally intimate relationships between the problems of sequential logic synthesis and sequential test generation are envisioned. A recently developed synthesis technique of constrained state assignment and logic optimization which ensures fully testable sequential machines is described briefly. >

Design process model in the Yorktown silicon compiler

Abstract: The automatic synthesis of an IBM 801 processing unit using the Yorktown Silicon Compiler is presented. The underlying design process model is explained showing the intermediate design stages, while emphasizing high-level issues. First, the principles of operations are translated manually into a high-level behavioral description. The system is decomposed by the designer into concurrent modules (in the 801, four pipeline stages). Structural synthesis automatically generates a circuit structure for each pipeline stage, including the control and the data path. The combinational logic is optimized globally during logic synthesis producing a multi-level implementation. The resulting size (in number of transistors) and the performance of the processor (estimated cycle time and cycles per instruction) are compared to a manual RT-level design.

Incremental-in-time algorithm for digital simulation

Abstract: Recently, an incremental algorithm (incremental-in-space algorithm) for digital simulation has been studied with good results in speeding up simulation. In this paper we present another algorithm (incremental-in-time algorithm) for incremental simulation of digital circuits. The incremental-in-space algorithm pessimistically resimulates the circuit components that could be affected by design changes throughout the simulation time frames. On the other hand, the incremental-in-time algorithm resimulates a circuit component only for the simulation time frames when its inputs or internal state variables make different state transitions from the previous simulation run. It maximally utilizes the past history thereby reducing the number of component evaluations to a minimum. Experimental results obtained for several practical circuits show speedups up to 30 times faster than conventional event-driven simulation.

CHAMP: concurrent hierarchical and multilevel program for simulation of VLSI circuits

Abstract: The design and implementation of a hierarchical switch-level simulator for complex digital circuits is discussed. The hierarchy is exploited to reduce the memory requirements of the simulation, thus allowing the simulation of circuits that are too large to simulate at the flat level. The algorithm used in the simulator operates directly on the hierarchical circuit description. Speedup is obtained through the use of high-level models. The simulator has been implemented on a SUN workstation and used to simulate a switch-level description of the Motorola 68000 microprocessor. >

A new layout optimization methodology for CMOS complex gates

Abstract: Efficient algorithms for the layout generation of CMOS complex gates are presented. Heuristics which use the concept of delayed binding are introduced. An optimized net list is decided during the layout generation phase, rather than before. Examples are given showing that this approach can achieve a considerable improvement over previous ones. >

A modified approach to two-level logic minimization

Abstract: A methodology in which it is not necessary to compute the entire offset is presented, that still provides a global picture. This scheme has been implemented in ESPRESSO with an interface to the multilevel minimization environment MIS. Initial results show that for functions for which the ratio of the size of the cover to the size of the don't care set is small, the new approach is much faster. The initial interest was to use this mainly in a multilevel logic synthesis system where the desired don't care sets are typically large. Some results in this environment are given, and the new scheme is compared with ESPRESSO. >

Simulating digital circuits with one bit per wire

Abstract: An algorithm to simulate synchronous digital logic circuits in space proportional to one bit per wire, as long as the specification has a hierarchical nature, is described. An entire simulation might fit in the fast cache of some computers. The simulation algorithm is simple to implement, and runs relatively quickly. Although the algorithm has a quadratic worst-case running time, empirical results show that the running time for typical circuits is close to linear. The algorithm is reasonably time-efficient in absolute terms (a few microseconds per gate), although somewhat slower than recently developed event-driven or straight-line simulators, and much slower than word-parallel straight-line compiled simulators. In effect, the algorithm produces behavioral simulators automatically from a circuit description: each module is a subroutine that may be invoked from other parts of the circuit. >