Showing papers on "Digital electronics published in 1991"

Programming in VLSI: from communicating processes to delay-insensitive circuits

Abstract: : see report With chip size reaching one million transistors. the complexity of VLSI algorithms -i.e., algorithms implemented as digital VLSI circuits is approaching that of software algorithms i.e., algorithms implemented as code for a stored-program computer. Yet design methods for VLSI algorithms lag far behind the potential of the technology. Since a digital circuit is the implementation of a concurrent algorithm. we propose a concurrent programming approach to digital VLSI design. The circuit to be designed is first implemented as a concurrent program that fulfills the logical specification of the circuit. The program is then compiled manually or automatically into a circuit by applying semantic-preserving program transformations. Hence, the circuit obtained is correct by construction. The main obstacle to such a method is finding an interface that provides a good separation of the physical and algorithmic concerns. Among the physical parameters of the implementation, timing is the most difficult to isolate from the logical design. because the timing properties of a circuit are essential not only to its real-time behavior but also to its logical correctness if the usual synchronous techniques are used to implement sequencing. For this reason. delay-insensitive techniques are particularly attractive for VLSI synthesis. A circuit is delay-insensitive when its correct operation is independent of any assumption on delays in operators and wires except that the delays be finite [17]. Such circuits do not use a clock signal or knowledge about delays. Let us clarify a matter of definitions right away: The class of entirely delay insensitive circuits is very limited. Different asynchronous techniques distinguish themselves in the choice of the compromises about delay-insensitivity. Speed-independent techniques assume that delays in gates are arbitrary, but that there are no delays in wires.

On variable ordering of binary decision diagrams for the application of multi-level logic synthesis

Abstract: We have developed multi-level logic minimization programs using Binary Decision Diagram (BDD). Here we present variable ordering methods of BDD. The variable ordering algorithm for two-level circuits is based on cover patterns and selects most binate variables first, and the one for multi-level circutis is based on depth first traverse of circuits. In both cases, the acquired variable orderings are optimized by exchanging a variable with its neighbor in the ordering.

Building and using a highly parallel programmable logic array

Abstract: A two-slot addition called Splash, which enables a Sun workstation to outperform a Cray-2 on certain applications, is discussed. Following an overview of the Splash design and programming, hardware development is described. The development of the logic description generator is examined in detail. Splash's runtime environment is described, and an example application, that of sequence comparison, is given. >

Retiming and resynthesis: optimizing sequential networks with combinational techniques

Abstract: Sequential networks contain combinational logic blocks separated by registers. Application of combinational logic minimization techniques to the separate logic block results in improvement that is restricted by the placement of the registers; information about logical dependencies between blocks separated by registers is not utilized. Temporarily moving all the registers to the periphery of a network provides the combinational logic minimization tools with a global view of the logic. A technique is proposed for optimizing a sequential network by moving the registers to the boundary of the network using an extension of retiming, resynthesizing the combinational logic between the registers using existing logic minimization techniques, and replacing the registers throughout the network using retiming algorithms. >

Performance Analysis and Optimization of Asynchronous Circuits

Abstract: Analytical techniques are developed to determine the performance of asynchronous digital circuits. These techniques can be used to guide the designer during the synthesis of such a circuit, leading to a high-performance, efficient implementation. Optimization techniques are also developed that further improve this implementation by determining the optimal sizes of the low-level devices (CMOS transistors) that compose the circuit. In order to determine the performance of an asynchronous circuit, it is first translated into an event-rule (ER) system, an abstract representation of the time dependencies (rules) between the primitive actions (events) of the circuit. This translation can be done from any of several different intermediate representations including: (i) a communicating sequential processes (CSP) program, (ii) a handshaking expansion, a refinement of the original CSP program in which all communication actions are replaced by explicit manipulations of boolean variables, (iii) a production rule set, a refinement of the handshaking expansion in which all sequencing is implemented by restricting concurrency, and (iv) a CMOS transistor network, a final representation from which the circuit can be fabricated. The analysis techniques are based on linear programming and provide an accurate approximation of the absolute time at which each event in an ER system occurs. Efficient algorithms for performing this approximation are developed and proven correct. Numerous examples are provided. This approximation can be represented as a formula expressing the performance of the circuit in terms of certain design variables, such as the widths of the transistors in the final CMOS network. This formula can be evaluated at particular width values and thus can be used to determine the performance of a particular realization of the circuit. Furthermore, using the techniques of convex programming, optimal transistor widths can be determined. The analysis techniques are applied to several large examples. Several implementations of first-in-first-out buffers are compared. A handshaking-expansion-level analysis of a simplified version of the Caltech Asynchronous Microprocessor is provided.

Improved logic synthesis algorithms for table look up architectures

Abstract: The authors address the problem of synthesis for a popular class of programmable gate array architecture-the table look-up architectures. These use lookup table memories to implement logic functions. The authors present improved techniques for minimizing the number of table look up blocks used to implement a combinational circuit. On average, the results obtained on a set of benchmarks are 15-29% better than results obtained by previous approaches. >

High-frequency equivalent circuit of GaAs FETs for large-signal applications

Abstract: The application of GaAs field effect transistors in digital circuits requires a valid description by an equivalent circuit at all possible gate and drain bias voltages for all frequencies from DC up to the gigahertz range. An equivalent circuit is presented which takes into account the gate current of positively biased transistors as well as the symmetrical nature of the devices at low drain voltages. A fast method of determining the elements of the equivalent circuit at all bias points without frequency limitations is presented. Direct computation from analytical expressions, without iteration, allows this parameter extraction procedure to be used for real-time on-wafer parameter extraction. Large-signal calculations are possible by inserting the voltage dependences evaluation for the elements into suitable simulation programs, such as SPICE. >

Synthesis of Asynchronous VLSI Circuits

Abstract: : With chip size reaching one million transistors. the complexity of VLSI algorithms-i.e., algorithms implemented as a digital VLSI circuit-is approaching that of software algorithms i.e., algorithms implemented as code for a stored-program computer. Yet design methods for VLSI algorithms lag far behind the potential of the technology. Since a digital circuit is the implementation of a concurrent algorithm, we propose a concurrent programming approach to digital VLSI design. The circuit to be designed is first implemented as a concurrent program that fulfills the logical specification of the circuit. The program is then compiled manually or automatically-into a circuit by applying semantic-preserving program transformations. Hence, the circuit obtained is correct by construction. The main obstacle to such a method is finding an interface that provides a good separation of the physical and algorithmic concerns. Among the physical parameters of the implementation, timing is the most difficult to isolate from the logical design, because the timing properties of a circuit are essential not only to its real time behavior but also to its logical correctness if the usual synchronous techniques are used to implement sequencing. For this reason, delay. insensitive' techniques are particularly attractive for VLSI synthesis. A circuit is delay-insensitive when its correct operation is independent of any assumption on delays in operators and wires except that the delays be finite. Such circuits do not use a clock signal or knowledge about delays. Let us clarify a matter of definitions right away: It has been proved in that the class of entirely delay-insensitive circuits is very limited. Different asynchronous techniques distinguish themselves in the choice of the compromises to delay-insensitivity.

Synchronous logic synthesis: algorithms for cycle-time minimization

Abstract: A novel approach to logic synthesis of digital synchronous circuits is presented. A model for synchronous circuits that supports logic transformations aimed at optimizing the circuit performance is presented. Previous synthesis approaches attacked this problem by separating the combinational logic from the registers and by applying circuit transformations to the combinational component only. It is shown how to optimize concurrently the circuit equations and the register position by a set of algorithms based on logic transformations. Experimental results on benchmark circuits are reported. >

CMOS video cameras

Abstract: A single chip CMOS video camera is presented, along with design technique and characterization results. The chip comprises a 312*287 pixel photodiode array together with all the necessary sensing, addressing and amplifying circuitry, as well as a 1000 gate logic processor, which implements synchronization timing to deliver a fully-formatted composite video signal and a further 1000 gate logic processor, which implements automatic exposure control over a wide range. There are also simple solutions for gamma correction and test. >

Implementation of PRML in a rigid disk drive

Abstract: Describes the channel architecture, IC technology, and integration solutions used in implementing the IBM 0681 disk drive data channel. A brief description of the 0681 disk drive is given along with a block representation of the data channel. Particular focus is placed on the major channel functions: equalization, data coding and detection, gain and timing recovery, and write circuitry. Both the analog and adaptive digital equalizer sections used in the channel are described. The 0681 channel uses an IBM mixed-mode IC technology to implement all channel functions. This IC process is illustrated, along with the partial-response maximum-likelihood (PRML) chip layout. Attention is also given to the hybrid nature of the PRML channel; many channel functions are implemented using a combination of both analog and digital circuits. >

Performance directed synthesis for table look up programmable gate arrays

Abstract: The authors address the problem of delay optimization for programmable gate arrays. The main considerations are the number of levels in the circuit and the wiring delay. The authors propose a two-phase approach: the first phase involves delay optimizations during logic synthesis before placement, while the second uses logic resynthesis in the case of a timing-driven placement technique. Results and comparisons on benchmarks are presented. >

Method and apparatus for the correlation of sample bits of spread spectrum radio signals

Abstract: A spread spectrum receiver correlator for a with filters matched to transmitter chip codes are implemented in digital circuits along with a digital circuit for acquisition and tracking of the arrival times of the chip codes The digital circuit implementations are used for the noncoherent demodulation of pulse position spread spectrum modulation signals where the pulse is a carrier modulator by a chip code and for the noncoherent demodulation of multiple chip code modulation signals where each information symbol is represented by one of several chip codes modulating a carrier

Mixed mode analog/digital programmable interconnect architecture

Abstract: A user-programmable integrated circuit includes an analog portion containing user-configurable analog circuit modules, a digital portion containing user-configurable digital circuit modules, an interface portion containing user-configurable interface circuits for conversion of signals from analog to digital form and from digital to analog form, and a user-configurable interconnection and input/output architecture.

Analysis of digital circuits through symbolic reduction

Abstract: The authors describe a semi-algorithmic method to extract finite-state models from an analog circuit-level model by means of homomorphic (behavior preserving) transformations. Properties to be verified are defined by omega -automata. Efficient algorithms for testing language containment of automata can then be applied to verify properties of the finite-state models. Proof of the property in the finite-state model guarantees the property in the analog circuit-level model over a continuous range of input waveforms and circuit parameters. While in practice this method applies directly only to smaller circuit components, it can be used to analyze larger circuits as well by deriving a hierarchy of increasingly abstract models, through repeated applications of homomorphic transformations. Examples of extraction, homomorphism, and verification are described. >

Fault modeling for the testing of mixed integrated circuits

Abstract: The goal of the research described in this paper is to introduce a fault-modeling technique for simulating defective analog components in Mixed Analog/Digital Integrated Circuits. The proposed fault- modeling strategy has been implemented to develop analog fault models representing the effect of spot defects in CMOS circuits. Results from an initial study of opamps are summarized and detailed results from onc example are included as an illustration of the fault- modeling process. 1 Introduction Application of analog components within large digital systems - a typical configuration in modern mixed analog/digital IC's - generates many new challenges in both design and testing areas (l), (2), (3), (4). EspccialIy difficult to solve are testing problems due to the observability limitations caused by the nature of the boundary between the digital and analog components of mixed IC's. Although there are many mixcd IC testing problems, this paper focuses on only one of them - a strategy of fault simulation. More specifically, this paper introduces a fault- modeling methodology which could be applied to capture the malfunctioning of analog components in mixed IC's. The goal of the reported research is to develop fault models that enable efficient simulation of the entire mixed IC by using a technique that is as close as possible to traditional digital circuit simulation techniques. Hence, this paper concentrates solely on the fault- modeling technique. It is organized in the following way. In Section 2, the general fault-modeling methodology developed for analog components of mixed IC's is introduced. In Section 3, an implementation of this methodology for CMOS technology is described in morc detail. Finally, in Section 4, an attempt to generalize obtained results is made in order to determine the practicality of the proposed fault-modeling methodology. This section also gives a list of problems to be solved in the subsequent research dealing with testing of mixcd analog/digital integrated circuits.

Accurate modeling and simulation of bridging faults

Abstract: A transistor-level examination of bridging faults and the resulting logic-level bridging fault model are described. Experiments with simulations and silicon demonstrate its accuracy. It is shown how to determine the logic value resulting from a bridging fault. This leads to a novel approach for test pattern generation and fault simulation. It is pointed out that the voting model accurately describes the behavior of shorted nodes in CMOS custom digital circuits. The logic value of shorted nodes is equal to the logic value output by the circuit with the most current drive. The threat of an intermediate voltage is very slight; therefore, bridging faults result in valid logic values on the shorted nodes. >

Dynamic degradation in MOSFET's. II. Application in the circuit environment

Abstract: For pt.I, see ibid., vol.38 no.8, pp.1852-1858, Aug. 1991. The physical effects discussed in Pt.I are classified with respect to real operation of devices in circuits from an engineer's viewpoint. Stress results from different kinds of logic stages are discussed and relations set up between static and dynamic lifetimes. It is shown that within certain limited error boundaries, the static approach is essentially valid as long as stress conditions are considered that are oriented to operation in digital logic. The transmission gate is investigated separately, because in this case specific phenomena caused by bidirectional stress must be considered. >

Sigma delta modulator

Abstract: A separate filter circuit is inserted between the D/A converter and the summing junction in the feedback path of a conventional sigma delta modulator. This additional filter allows control of the quantization noise transfer function profile independently of the forward signal transfer function. By proper tailoring of the transfer functions a third or higher order modulator can be constructed without instability developing. The modulator can also be constructed as a completely digital circuit and used as a noise shaping circuit in a digital digital-to-analog converter.

Extraction of gate level models from transistor circuits by four-valued symbolic analysis

Abstract: The program TRANALYZE generates a gate-level representation of an MOS transistor circuit. The results model contains only four-valued unit and zero delay logic primitives, suitable for evaluation by conventional gate-level simulators and hardware simulation accelerators. TRANALYZE has the same generality and accuracy as switch-level simulation, generating models for a wide range of technologies and design styles, while expressing the detailed effects of bidirectional transistors, stored charge, and multiple signal strengths. It produces models with size comparable to ones generated by hand. >

Delay testing of digital circuits by output waveform analysis

Abstract: A new method for delay fault testing of digital circuits is presented. Unlike catastrophic failures that simply have incorrect steady-state logic values at the circuit outputs, delay faults change the shape of the output waveforms by moving the signal transitions in time. Therefore, since the output waveforms contain information about the circuit delays, instead of only latching the outputs at the sampling time, the output waveforms between samples are analyzed as well. Two classes of output waveform analysis are discussed. In the first technique, the output waveform is observed for any changes after the sampling time, since in a fault-free circuit, the outputs are expected to have stabilized at the desired logic values. In the second technique, information is extracted from the faulty and fault-free waveforms before the sampling time, and compared for any differences. Circuits for the waveform analyzers are presented to show that the method is feasible, and experimental results are given.

Technology mapping for electrically programmable gate arrays

Abstract: We describe a new approach for technology mapping of electrically programmable gate arrays (EPGAs). These are arrays of uncommitted modules, where the personalization is achieved by fuselantifuse technology and can be modeled by stuck-at and/or bridging inputs. We present a matching algorithm that determines whether a portion of a combinational logic circuit can be implemented by personalizing a module. The algorithm has the advantage of considering the entire library of functions that can be implemented by the module without resorting to an explicit enumeration. The benefits are an increased efficiency in technology mapping, as well as portability to different types of electrically programmable gate arrays. Experimental results on standard benchmarks are reported.

The circuit designer's companion

Abstract: Part 1 Grounding and wiring: grounding wiring and cables transmission lines. Part 2 Printed circuits: board types design rules surface protection surface mount sourcing boards and artwork. Part 3 Passive components: resistors potentiometers capacitors inductors crystals. Part 4 Active components: diodes thyristors and triacs bipolar transistors junction field effect transistors MOSFETs. Part 5 Linear integrated circuits: the ideal op-amp the practical op-amp comparators voltage references. Part 6 Digital circuits: logic ICs interfacing microprocessor watchdogs and supervision software techniques. Part 7 Power supplies: general input and output parameters abnormal conditions mechanical requirements batteries. Part 8 Electromagnetic compatibility: the need for EMC EMC legislation and standards interference coupling mechanisms circuit design and layout shielding filtering cables and connectors EMC design checklist. Part 9 General product design: safety design for production testability reliability thermal management.

Integrated optical inverter using light amplifying optical switch (LAOS)

Abstract: An integrated optical inverter is demonstrated. Experimental results show good static input/output characteristics and an on/off ratio suitable for integrated optical logic. The simplicity of this circuit allows compact integration.

Electronic circuits : design and applications

Abstract: This text on electronic circuit design and application, has been given a new title as it has been updated and widened in scope. Written both for the student and the practising engineer and scientist, the book covers major aspects and applications of modern analogue and digital circuit design. Part I concentrates on analogue and digital circuits, on operational amplifiers, combinatorial and sequential logic and memories. Part II is application-oriented. Each chapter offers various solutions to a given problem, and is designed to enable the reader to understand ready-made circuits and/or to proceed reasonably quickly from theory to a working circuit. The design approach is often illustrated by an example. Analogue applications cover such topics as analogue computing circuits. The digital sections deal with AD and DA conversion, digitial computing circuits, microprocessors and digital filters.

Design of robustly testable combinational logic circuits

Abstract: An integrated approach to the design of combinational logic circuits in which all path delay faults and multiple line stuck-at, transistor stuck-open faults are detectable by robust tests is proposed. Robustly testable static CMOS primitive logic circuit designs are presented for any arbitrary combinational logic function. They require no special gates, and fan-in and fan-out constraints do not affect the designs. Extra controllable inputs or additional hardware to achieve testability was not used. It is demonstrated that the method guarantees the design of CMOS logic circuits in which all path delay faults are locatable. >