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Showing papers on "Digital electronics published in 1993"


Book
01 Mar 1993
TL;DR: In this paper, the high speed properties of logic gates measurement techniques are discussed, including transmission lines, ground planes and layer stacking terminations, connectors, ribbon cables, clock distribution clock oscillators, etc.
Abstract: Fundamentals high speed properties of logic gates measurement techniques transmission lines ground planes and layer stacking terminations VIAS power systems connectors ribbon cables clock distribution clock oscillators.

639 citations


Journal ArticleDOI
Farid N. Najm1
TL;DR: It is shown how the density values at internal nodes can be used to study circuit reliability by estimating theaverage power and ground currents; the average power dissipation; the susceptibility to electromigration failures; and the extent of hot-electron degradation.
Abstract: Noting that a common element in most causes of runtime failure is the extent of circuit activity, i.e. the rate at which its nodes are switching, the author proposes a measure of activity, called the transition density, which may be defined as the average switching rate at a circuit node. An algorithm is also presented to propagate density values from the primary inputs to internal and output nodes. To illustrate the practical significance of this work, it is shown how the density values at internal nodes can be used to study circuit reliability by estimating the average power and ground currents; the average power dissipation; the susceptibility to electromigration failures; and the extent of hot-electron degradation. The density propagation algorithm has been implemented in a prototype density simulator which is used to assess the validity and feasibility of the approach experimentally. The results show that the approach is very efficient, and makes possible the analysis of VLSI circuits. >

430 citations


Journal ArticleDOI
TL;DR: Methods for the cost-effective design of combinational and sequential self-checking functional circuits and checkers are examined and the area overhead for all proposed design alternatives is studied in detail.
Abstract: Self-checking circuits can detect the presence of both transient and permanent faults. A self-checking circuit consists of a functional circuit that produces encoded output vectors and a checker that checks the output vectors. The checker has the ability to expose its own faults as well. The functional circuit can be either combinational or sequential. A self-checking system consists of an interconnection of self-checking circuits. The advantage of such a system is that errors can be caught as soon as they occur; thus, data contamination is prevented. Methods for the cost-effective design of combinational and sequential self-checking functional circuits and checkers are examined. The area overhead for all proposed design alternatives is studied in detail. >

185 citations


Journal ArticleDOI
TL;DR: In this paper, a 2.5- mu m 1000-A/cm/sup 2/Nb trilayer technology was used to construct a simple RSFQ circuit including an inverter, confluence buffer, and Josephson transmission line.
Abstract: Several novel circuits of the rapid single-flux-quantum (RSFQ) family of Josephson-junction digital devices have been designed, fabricated using a 2.5- mu m 1000-A/cm/sup 2/ Nb trilayer technology, and tested at low frequencies. Numerical simulation and measurements have shown that these circuits have considerably wider parameter margins, due to application of several novel design methods. The authors have also carried out an experiment to measure the rate of errors in a simple RSFQ circuit including an inverter, confluence buffer, and Josephson transmission line. Near the middle of the parameter window at 4.2 K, the error probability was definitely lower than 3*10/sup -15/ per logic operation, despite experimentation with rudimentary shielding and filtering. >

140 citations


Journal ArticleDOI
TL;DR: In this article, it is argued that the most reliable and reasonable criterion is to maximize the product of the two noise margins, which is equivalent to maximizing the area of a rectangle embedded within the loop formed by the transfer curves of an inverter pair.
Abstract: Techniques for evaluating the noise margin for families of digital logic circuits are discussed and evaluated. It is shown that the technique of evaluating the -1 slope points on the inverter transfer function as used in most modern textbooks is not a valid and reliable approach to evaluating noise margin values. It is argued that the most reliable and reasonable criterion is to maximize the product of the two noise margins. This is equivalent to maximizing the area of a rectangle embedded within the loop formed by the transfer curves of an inverter pair. Most of the material presented can be found in the early literature on noise margin. However, because of the widespread use of the -1 slope criterion in modern textbooks, it is believed that a reexamination of basic approaches to noise margins is in order. >

131 citations


Journal ArticleDOI
TL;DR: Algorithms to automatically realize delays in combinational logic circuits to achieve wave pipelining are presented and the algorithms adjust gate speeds and insert a minimal number of active delay elements to balance input-output path lengths in a circuit.
Abstract: Algorithms to automatically realize delays in combinational logic circuits to achieve wave pipelining are presented. The algorithms adjust gate speeds and insert a minimal number of active delay elements to balance input-output path lengths in a circuit. For both normal and wave-pipelined circuits, the algorithms also optimally minimize power under delay constraints. The authors analyze the algorithms and comment on their implementation. They report experimental results, including the design and testing of a 63-bit population counter in CML bipolar technology. A brief analysis of circuit technologies shows that CML and super-buffered ECL without stacked structures are well suited for wave pipelining because they have uniform delay. Static CMOS and ordinary ECL including stacked structures and emitter-followers do have some delay variations. A high degree of wave pipelining is still possible in those technologies if special design techniques are followed. >

107 citations


PatentDOI
TL;DR: In this article, a hearing aid with digital, electronic compensation for acoustic feedback comprises a microphone (5), a preamplifier (7), a digital compensation circuit (3), an output amplifier (9) and a transducer (11).
Abstract: A hearing aid with digital, electronic compensation for acoustic feedback comprises a microphone (5), a preamplifier (7), a digital compensation circuit (3), an output amplifier (9) and a transducer (11). The digital circuit (3) comprises a noise generator (33) for the insertion of noise, and an adjustable, digital filter (27) for the adaptation of the feedback signal. The adaptation takes place using a correlation circuit (31). The circuit further comprises a digital circuit (210) which monitors the loop gain and regulates the hearing aid amplification via a digital summing circuit (211), so that the loop gain is less than a constant K. The circuit further comprises a digital circuit (79) which carries out a statistical evaluation of the filter coefficients in the correlation circuit, and changes the feedback function in accordance with this evaluation.

100 citations


Patent
09 Aug 1993
TL;DR: In this paper, a vehicle collision avoidance radar system using digital signal processing techniques including a transmit section (202) that generates a two-channel transmit frequency and a Schottky diode mixer (208) generates a difference signal having a frequency equal to the transmit frequency minus the receive frequency.
Abstract: A vehicular collision avoidance radar system using digital signal processing techniques including a transmit section (202) that generates a two channel transmit frequency. An antenna (210) both transmits the transmit signal and receives a reflected receive signal. A Schottky diode mixer (208) generates a difference signal having a frequency equal to the transmit frequency minus the receive frequency. A signal switch (304) in a front end electronics section (300) time demultiplexes and samples the channel 1 and channel 2 signals. The samples are coupled to a two-channel analog to digital (A/D) converter (310). A digital electronics section (500) receives the digital information and performs a Fast Fourier Transform (FFT) on each channel of digital data to determine relative speed and range of a target based upon the frequency and the difference in phase of the two channels. The digital electronics section also receives information regarding the status of vehicle operation and/or controls to determine the degree of danger presented by an identified target.

95 citations


Proceedings ArticleDOI
24 May 1993
TL;DR: An algorithm for mapping multiple-valued functions to such an array is presented and it works in the functional domain and does not require the synthesis and optimization of a conventional network prior to technology mapping.
Abstract: A brief overview of past progress in multiple-valued logic design is presented. The methods are considered with respect to the likely development of multiple-valued field programmable gate arrays. Look-up table based arrays are considered in some detail and an algorithm for mapping multiple-valued functions to such an array is presented. This algorithm uses reduced order multiple-valued decision diagrams, an extension of R.E. Bryant's (1986) well-studied structure for binary functions. The algorithm works in the functional domain and does not require the synthesis and optimization of a conventional network prior to technology mapping. >

91 citations


Proceedings ArticleDOI
01 Jul 1993
TL;DR: This paper describes a method for the diagnosis and correction of logic design errors in an erroneous gate-level implementation that is robust and covers more types of design errors than previous work.
Abstract: This paper describes a method for the diagnosis and correction of logic design errors in an erroneous gate-level implementation. Our method is robust and covers more types of design errors than previous work. Our major contribution is providing significant improvement in efficiency, which is most crucial for practical applications. The notion of immediate dominator set is introduced for efficient error diagnosis. Implicit enumeration of the function space is developed for achieving fast error correction. Experimental results for a set of ISCAS and MCNC benchmark circuits demonstrate the effectiveness of the proposed techniques. Circuits with thousands of gates can be corrected in minutes.

62 citations


Journal ArticleDOI
TL;DR: In this article, a CMOS circuit implementation of a functionally complete multiple-valued logic (MVL) set of operators is proposed, which consists of literal, cycle, complement of literal and complement of cycle, min, and tsum operators.
Abstract: A CMOS circuit implementation of a functionally complete multiple-valued logic (MVL) set of operators is proposed. The set consists of literal, cycle, complement of literal, complement of cycle, min, and tsum operators. In all of the circuits, multiple-valued logic levels are represented in terms of current values. Binary voltage signals are generated inside the circuits using a threshold circuit element. These binary voltage signals are used to generate control signals for switches to realize appropriate current levels for the desired multiple-valued logic levels. Transient analysis simulations (using HSPICE) to verify the functionality of the designed circuits and the effect of variation in process parameters are also reported. >

Journal ArticleDOI
TL;DR: The proposed dynamic ternary gates do not dissipate DC power and have full voltage swings, and the structure has the advantages of higher operating frequency, less latency, and lower device count as compared with the conventional binary parallel pipelined multiplier.
Abstract: Dynamic CMOS ternary logic circuits that can be used to form a pipelined system with nonoverlapped two-phase clocks are proposed and investigated. The proposed dynamic ternary gates do not dissipate DC power and have full voltage swings. A circuit structure called the simple ternary differential logic (STDL) is also proposed and analyzed, and an optimal procedure is developed. An experimental chip has been fabricated in a 1.2- mu m CMOS process and tested. A binary pipelined multiplier has been designed, using the proposed dynamic ternary logic circuits in the interior of the multiplier for coding of radix-2 redundant positive-digit number. The structure has the advantages of higher operating frequency, less latency, and lower device count as compared with the conventional binary parallel pipelined multiplier. The advantages of the circuits over other dynamic ternary logic circuits are shown. >

Journal ArticleDOI
S. Mohan1, Pinaki Mazumder1, George I. Haddad1, R.K. Mains1, J. P. Sun1 
01 Dec 1993
TL;DR: In this paper, the authors introduce a new set of relative costs of various basic gates, and reevaluation of the logic in the light of these new cost functions leads to ultrafast and compact designs.
Abstract: New quantum electronic devices such as resonant tunnelling diodes and transistors have negative differential resistance characteristics that can be exploited to design novel high-speed circuits. The high intrinsic switching speed of these devices, combined with the novel circuit structures used to implement standard logic functions, leads to ultrafast computing circuits. The new circuit structures presented here provide extremely compact implementations of functions such as carry generation and addition. The most significant impact of these circuits on the field of logic design is the introduction of a totally new set of relative costs of various basic gates; reevaluation of the logic in the light of these new cost functions leads to ultrafast and compact designs.

Journal ArticleDOI
TL;DR: The modified PWCTC algorithm, PW CTC-W, which handles circuits with feedback, is introduced and shown to be superior to the dynamic-windowing scheme and to be insensitive to the level of strongly concerned component (SCC) hierarchy.
Abstract: The authors introduce ILLIADS as a fast MOS timing and reliability simulator for very large digital MOS circuits. The use of the proposed general circuit primitive not only provides better accuracy but also significantly reduces the simulation time. The use of an analytic solution embedded in the simulation engine improves both the simulation speed and the accuracy. Postponing the waveform approximation process provides better waveform approximation even for non-fully-switching waveforms and glitches. The channel length modulation effect is captured accurately in fast timing simulation with only 10% of speedup tradeoff. It is also shown that ILLIADS manifests the charge sharing problem. The modified PWCTC algorithm, PWCTC-W, which handles circuits with feedback, is introduced and shown to be superior to the dynamic-windowing scheme. It also does not manifest the window-growing problem and is insensitive to the level of strongly concerned component (SCC) hierarchy. The use of this algorithm keeps the speedup of ILLIADS over SPICE for circuits with feedbacks at the same level as that for combinational circuits. >

Journal ArticleDOI
TL;DR: In this article, a high-speed digital logic family based on heterojunction bipolar transistors (HBTs) and resonant tunneling diodes (RTDs) is proposed.
Abstract: A high-speed digital logic family based on heterojunction bipolar transistors (HBTs) and resonant tunneling diodes (RTDs) is proposed. The negative differential resistance of RTDs is used to significantly decrease the static power dissipation. SPICE simulations indicate that propagation delay time below 150 ps at 0.09-mW static power per gate should be obtainable. >

Journal ArticleDOI
TL;DR: A unified framework for the specification and computation of don't care conditions for combinational and synchronous multiple-level digital circuits is presented and it is shown that the don't cared conditions for the gate optimization represent the bound on this perturbation.
Abstract: A unified framework for the specification and computation of don't care conditions for combinational and synchronous multiple-level digital circuits is presented. Circuits are characterized in terms of graphs, logic functions and don't care conditions induced by the external and internal interconnections. The replacement of a gate in a synchronous logic network is modeled by a perturbation of the corresponding logic function, and it is shown that the don't care conditions for the gate optimization represent the bound on this perturbation. Algorithms to compute such don't care conditions in both the combinational and synchronous case are presented. The implementation of the algorithms and the experimental results are discussed. >

Journal ArticleDOI
TL;DR: In this article, the shape of high-bandwidth signals in CMOS circuits has been studied in the sub-nanosecond range, for instance, the rise time of a clock edge or the detailed shape of noise pulses.
Abstract: In this Letter we present a technique to measure details of the shape of high-bandwidth signals in CMOS circuits. This technique allows us to study quantities in the subnanosecond range as, for instance, the rise time of a clock edge or the detailed shape of noise pulses.

Proceedings ArticleDOI
01 Jul 1993
TL;DR: This work presents a novel approach to analog circuit fault simulation and test generation by mapping the circuit and circuit-level faults to the discrete domain and performing an efficient fault simulation on this discretized circuit.
Abstract: The areas of analog circuit fault simulation and test generation have not achieved the same degree of success as their digital counterparts owing to the difficulty in modeling the more complex analog behavior. We present a novel approach to this problem by mapping the circuit and circuit-level faults to the discrete domain. An efficient fault simulation is then performed on this discretized circuit for the given input test waveform.

Journal ArticleDOI
L.T. Wurtz1
TL;DR: In this article, a built-in self-test (BIST) structure is presented which provides controllability and observability to analog circuits under test with significantly reduced hardware overhead compared to previously reported methods.
Abstract: A built-in self-test (BIST) structure is presented which provides controllability and observability to analog circuits under test with significantly reduced hardware overhead compared to previously reported methods. The test structure is equally applicable to digital circuits, and lends itself to automated insertion into circuits under test. >

Proceedings ArticleDOI
16 Aug 1993
TL;DR: An FPGA logic block architecture that features MVL current-mode CMOS circuitry is proposed that combines the lookup-table and multiplexer approaches found in commercial FPGAs, and provides additional versatility through its current- mode operation.
Abstract: This paper considers the applicability of multiple-valued logic (MVL) circuits in implementation of field-programmable gate arrays (FPGAs). It proposes an FPGA logic block architecture that features MVL current-mode CMOS circuitry. The logic block combines the lookup-table and multiplexer approaches found in commercial FPGAs, and provides additional versatility through its current-mode operation. >

Proceedings ArticleDOI
01 Jul 1993
TL;DR: A new partial input enumeration (PIE) algorithm is presented to resolve correlations and significantly improve the upper bound (in one case, reducing the error by 64% on a circuit with about 1,700 gates) and is applicable to large VLSI circuits.
Abstract: Currents flowing in the power and ground (P&G) lines of CMOS digital circuits affect both circuit reliability and performance by causing excessive voltage drops. Maximum current estimates are therefore needed in the P&G lines to determine the severity of the voltage drop problems and to properly design the supply lines to eliminate these problems. These currents, however, depend on the specific input patterns that are applied to the circuit. Since it is prohibitively expensive to enumerate all possible inputs, this problem has, for a long time, remained largely unsolved. In [1], we proposed a pattern-independent, linear time algorithm (iMax) that estimates an upper bound envelope of all possible current waveforms that result from the application of different input patterns to the circuit. While the bound produced by iMax is fairly tight on many circuits, there can be a significant loss in accuracy due to correlations between signals internal to the circuit. In this paper, we present a new partial input enumeration (PIE) algorithm to resolve these correlations and significantly improve the upper bound (in one case, reducing the error by 64% on a circuit with about 1,700 gates). We also show good speed performance, analyzing circuits with more than 20,000 gates in about 2 hours on a SUN ELC. We demonstrate with extensive experimental results that the algorithm represents a good time-accuracy trade-off and is applicable to large VLSI circuits.

Journal ArticleDOI
TL;DR: A large-scale, dual-network architecture using wafer-scale integration (WSI) technology is proposed that allowed high-speed learning at more than 2 gigaconnections updated per second (GCUPS), the high fault tolerance of the neural network and proposed defect-handling techniques overcame the yield problem of WSI.
Abstract: A large-scale, dual-network architecture using wafer-scale integration (WSI) technology is proposed. By using 0.8 mu m CMOS technology, up to 144 self-learning digital neurons were integrated on each of eight 5 in silicon wafers. Neural functions and the back-propagation (BP) algorithm were mapped to digital circuits. The complete hardware system packaged more than 1000 neurons within a 30 cm cube. The dual-network architecture allowed high-speed learning at more than 2 gigaconnections updated per second (GCUPS). The high fault tolerance of the neural network and proposed defect-handling techniques overcame the yield problem of WSI. This hardware can be connected to a host workstation and used to simulating a wide range of artificial neural networks. Signature verification and stock price prediction have already been demonstrated with this hardware. >

Proceedings ArticleDOI
01 Jan 1993
TL;DR: A highly-flexible real-time-reconfigurable logic circuit implemented using a regular CMOS process, called soft-hardware logic (SHL), which can alter its logic function in real time according to external control signals with no hardware modification.
Abstract: A highly-flexible real-time-reconfigurable logic circuit implemented using a regular CMOS process is presented. The circuit, called soft-hardware logic (SHL), can alter its logic function (e.g. AND, OR, NAND, NOR, Exclusive OR, Exclusive NOR) in real time according to external control signals with no hardware modification. The circuit is one application of the neuron MOSFET (neuMOS or vMOS), a multiple-input functional MOS transistor simulating the function of biological neurons by a single device. The concept has been verified by experiments using test circuits fabricated by a standard double-polysilicon CMOS process. Details on the operational principle of the SHL circuit as well as design techniques are presented. One extension of this vMOS concept is a dynamic data-matching circuit in which rules for data matching are time-variable. Circuit operation has been verified by experiments. >

Journal ArticleDOI
09 May 1993
TL;DR: A mixed-signal, 7.0 Mbyte/s PRML (partial-response maximum likelihood) read/write channel is discussed in this paper.
Abstract: A mixed-signal, 7.0 Mbyte/s PRML (partial-response maximum likelihood) read/write channel is discussed in this paper. PR-IV (minimum signal bandwidth) for signal encoding is used, along with ML (maximum likelihood) detection to achieve superior error rate performance. Signal equalization is provided using a programmable ten-tap FIR (finite impulse response) digital filter. This read/write channel is implemented on a single chip using analog circuits and 20 K CMOS logic gates. The 7.5 mm square chip uses a 5 V, 1 /spl mu/m, BiCMOS process with a 6 GHz n-p-n and a 1 GHz p-n-p and is packaged in a 100-lead metal QFPK (quad flat pack). >

Patent
12 Oct 1993
TL;DR: In this paper, a digital input signal is first sampled as an analog signal and then processed using interpolative techniques to ascertain when the input signal crossed a hypothetical logic level threshold or pair of thresholds and when the signal was in one logic state or the other.
Abstract: Methods for producing logic signal displays for an instrument known as a "logic oscilloscope" are disclosed. A digital input signal is first sampled as an analog signal to produce multi-bit digital samples that are representative of the amplitude of the input signal over time. The multi-bit digital samples are then processed using interpolative techniques to ascertain when the input signal crossed a hypothetical logic level threshold or pair of thresholds and when the signal was in one logic state or the other. The resulting transition times and logic states are then used as the basis for generating a variety of digital displays, including logic timing diagrams, state table displays, and cursor readouts similar to those available in a logic analyzer. Setup and hold time violations and measurements may also be obtained using this information. In a pseudo-synchronous mode of operation, one logic signal is treated as a virtual clock signal, so that the states of other (data) signals are determined at times controlled by the active transitions of this clock signal. A cursor provides a digital readout of the logic value of one or more signals, whether they are displayed in analog form or logic timing diagram form or not shown on the screen at all.

Proceedings ArticleDOI
01 Jul 1993
TL;DR: A method which uses transistor reordering for the performance enhancement of CMOS circuits is presented and achieves significant reduction in propagation delays with little effect on layout area.
Abstract: A method which uses transistor reordering for the performance enhancement of CMOS circuits is presented. The proposed technique achieves significant reduction in propagation delays with little effect on layout area. The technique can be coupled with transistor sizing to achieve unbounded improvement in circuit delay, and it can be used to decrease dynamic power dissipation. In particular, excellent results have been achieved when the method is applied to data path circuits.

Journal ArticleDOI
T. Watanabe1, K. Kimura1, M. Aoki1, Takeshi Sakata1, K. Ito1 
TL;DR: A digital-chip architecture for a 10(6)-synapse neural network is proposed that runs on a 1.5-V dry cell to allow its use in portable equipment and to provide easy programmability and automatic refreshing.
Abstract: A digital-chip architecture for a 10/sup 6/-synapse neural network is proposed. It runs on a 1.5-V dry cell to allow its use in portable equipment. An on-chip DRAM cell array stores synapse weights digitally to provide easy programmability and automatic refreshing. A pitch-matched interconnection and a combinational unit circuit for summing product allow a tight layout. A dynamic data transfer circuit and the 1.5-V operation of the entire chip reduce the power dissipation, but the parallel processing nonetheless provides high speed at the 1.5-V supply. Estimated power dissipation of 75 mW and a processing speed of 1.37 giga connections per second are predicted for the chip. The memory and the processing circuits can be integrated on a 15.4-mm*18.6-mm chip by using a 0.5- mu m CMOS design rule. A scaled-down version of the chip that has an 8-kb DRAM cell array was fabricated, and its operation was confirmed. >

Proceedings Article
01 Jan 1993
TL;DR: The usefulness and power of fast mismatch analysis options within the network analysis environment are demonstrated and the physical connections introduced between local and global process variations lead to new procedures for calculating the overall tolerance ranges of the electrical characteristics.
Abstract: In contrast to digital circuits, the fabrication tolerance of electrical characteristics of analog integrated circuits depends highly on the local device matching accuracy. Especially for scaled structures down to the submicrometer range, the local statistical device parameter mismatching increases rapidly. As in network analysis programs (i.e., SPICE), statistical mismatch effects are not represented within the implemented device modeling; consequently no analysis options are available to compute their influence on electrical circuit characteristics in production

Proceedings ArticleDOI
Jiayuan Fang1, Y. Liu1, Yuzhe Chen1, Zhonghua Wu1, A. Agrawal 
20 Oct 1993
TL;DR: In this article, a new model for the simulation of power/ground plane noise which is simple in principle, accurate in its solutions, and applicable to various levels of high-speed digital electronics packaging, is given.
Abstract: A new model for the simulation of power/ground plane noise which is simple in principle, accurate in its solutions, and applicable to various levels of high-speed digital electronics packaging, is given. It is found that one can obtain accurate modeling of delta-I noise in power and ground planes without resorting to full-wave electromagnetic modeling. Sample results of the simulated delta-I noise with the method are shown. >

Journal ArticleDOI
TL;DR: The test synthesis of some combinational CMOS benchmark circuits illustrates the superiority of the CMOS fault models and their application to test pattern generation as compared with the classical stuck-at fault models.
Abstract: An arithmetic approach to extract the potential physical defects from the specific circuit layout of an integrated circuit is proposed. The defects subsequently are transformed into circuit faults and weighted according to their likelihood of occurrence. Based on these open and short faults extracted from CMOS layouts, an automatic test pattern generator is implemented. The test synthesis of some combinational CMOS benchmark circuits illustrates the superiority of the CMOS fault models and their application to test pattern generation as compared with the classical stuck-at fault models. >