Showing papers on "Digital electronics published in 1995"

Minimizing power consumption in digital CMOS circuits

Abstract: An approach is presented for minimizing power consumption for digital systems implemented in CMOS which involves optimization at all levels of the design. This optimization includes the technology used to implement the digital circuits, the circuit style and topology, the architecture for implementing the circuits and at the highest level the algorithms that are being implemented. The most important technology consideration is the threshold voltage and its control which allows the reduction of supply voltage without significant impact on logic speed. Even further supply reductions can be made by the use of an architecture-based voltage scaling strategy, which uses parallelism and pipelining, to tradeoff silicon area and power reduction. Since energy is only consumed when capacitance is being switched power can be reduced by minimizing this capacitance through operation reduction choice of number representation, exploitation of signal correlations, resynchronization to minimize glitching, logic design, circuit design, and physical design. The low-power techniques that are presented have been applied to the design of a chipset for a portable multimedia terminal that supports pen input, speech I/O and full-motion video. The entire chipset that performs protocol conversion, synchronization, error correction, packetization, buffering, video decompression and D/A conversion operates from a 1.1 V supply and consumes less than 5 mW. >

Optimizing and operating a time multiplexed programmable logic device

Abstract: A method of optimizing a time multiplexed programmable logic device (PLD) includes entering a circuit design for the PLD, mapping the design to the physical resources of the PLD (wherein the physical resources include configurable logic elements), determining an appropriate micro cycle for each configurable logic element in the design, placing the resources on the PLD, and connecting the resources Optimizing the design may include reducing the number of look up tables or reducing the logic depth of the look up tables If the configurable logic elements include sequential logic elements, then the optimizing step includes rescheduling the sequential logic elements A method of operating a time multiplexed PLD in a logic engine mode includes programming the PLD to implement a design in stages, wherein each stage is one configuration, sequencing the PLD through all the configurations, and storing the results of the logic performed in one configuration in a plurality of micro registers for use in subsequent configurations In one embodiment, the PLD includes a plurality of combinational elements and sequential logic elements, wherein the values stored by the sequential logic elements are stored in the micro registers

Pattern independent maximum current estimation in power and ground buses of CMOS VLSI circuits: Algorithms, signal correlations, and their resolution

Abstract: Currents flowing in the power and ground (P&G) buses of CMOS digital circuits affect both circuit reliability and performance by causing excessive voltage drops. Excessive voltage drops manifest themselves as glitches on the P&G buses and cause erroneous logic signals and degradation in switching speeds. Maximum current estimates are needed at every contact point in the buses to study the severity of the voltage drop problems and to redesign the supply lines accordingly. These currents, however, depend on the specific input patterns that are applied to the circuit. Since it is prohibitively expensive to enumerate all possible input patterns, this problem has, for a long time, remained largely unsolved. In this paper, we propose a pattern-independent, linear time algorithm (iMax) that estimates at every contact point, an upper bound envelope of all possible current waveforms that result by the application of different input patterns to the circuit. The algorithm is extremely efficient and produces good results for most circuits as is demonstrated by experimental results on several benchmark circuits. The accuracy of the algorithm can be further improved by resolving the signal correlations that exist inside a circuit. We also present a novel partial input enumeration (PIE) technique to resolve signal correlations and significantly improve the upper bounds for circuits where the bounds produced by iMax are not tight. We establish with extensive experimental results that these algorithms represent a good time-accuracy trade-off and are applicable to VLSI circuits. >

Digital Logic Circuit Analysis and Design

Abstract: 0. Introduction. 1. Number Systems and Codes. 2. Algebraic Methods for Analysis and Synthesis of Logic Circuits. 3. Simplification of Switching Functions. 4. Modular Combinational Logic. 5. Combinational Circuit Design with Programmable Logic Devices. 6. Introduction to Sequential Devices. 7. Modular Sequential Logic. 8. Analysis and Synthesis of Synchronous Sequential Circuits. 9. Simplification of Sequential Circuits. 10. Asychronous Sequential Circuits. 11. Sequential Circuits with Programmable Logic Devices. 12. Logic Circuit Testing and Testable Design. 13. Design Examples.

Low-power design techniques for high-performance CMOS adders

Abstract: A high-performance adder is one of the most critical components of a processor which determines its throughput, as it is used in the ALU, the floating-point unit, and for address generation in case of cache or memory access. In this paper, low-power design techniques for various digital circuit families are studied for implementing high-performance adders, with the objective to optimize performance per watt or energy efficiency as well as silicon area efficiency. While the investigation is done using 100 MHz, 32 b carry lookahead (CLA) adders in a 0.6 /spl mu/m CMOS technology, most techniques presented here can also be applied to other parallel adder algorithms such as carry-select adders (CSA) and other energy efficient CMOS circuits. Among the techniques presented here, the double pass-transistor logic (DPL) is found to be the most energy efficient while the single-rail domino and complementary pass-transistor logic (CPL) result in the best performance and the most area efficient adders, respectively. The impact of transistor threshold voltage scaling on energy efficiency is also examined when the supply voltage is scaled from 3.5 V down to 1.0 V. >

Possible performance of capacitively coupled single‐electron transistors in digital circuits

Abstract: We have carried out a theoretical analysis of the possible performance of single‐electron transistors with capacitive coupling in simple logic and memory circuits. Both resistively loaded and complementary transistors have been analyzed, with a detailed account of parasitic factors including thermal fluctuations and background charge variations. The analysis shows that at optimal values of the parameters including the background charge, the maximum operation temperature is close to 0.025e2/CkB, where C is the capacitance of the smallest tunnel junction. At T∼0.01e2/CkB the parameter margins are relatively wide; for the structures with 2‐nm minimum feature size, the latter temperature is close to 77 K. A typical margin for background charge fluctuations is on the order of 0.1e; these fluctuations may be a major obstacle for practical ultradense single‐electron circuits.

Fast discrete function evaluation using decision diagrams

Abstract: An approach for fast discrete function evaluation based on multi-valued decision diagrams (MDD) is proposed. The MDD for a logic function is translated into a table on, which function evaluation is performed by a sequence of address lookups. The value of a function for a given input assignment is obtained with at most one lookup per input. The main application is to cycle-based logic simulation of digital circuits, where the principal difference from other logic simulators is that only values of the output and latch ports are computed. Theoretically, decision-diagram based function evaluation offers orders-of-magnitude potential speedup over traditional logic simulation methods. In practice, memory bandwidth becomes the dominant consideration on large designs. We describe techniques to optimize usage of the memory hierarchy.

Combinational ATPG theorems for identifying untestable faults in sequential circuits

Abstract: We give two theorems for identifying untestable faults in sequential circuits. The first, the single-fault theorem, states that if a single fault in a combinational array is untestable then that fault is untestable in the sequential circuit. The array replicates the combinational logic and can have any finite length. We assume that the present state inputs of the left-most block are completely controllable. The next state outputs of the right-most block are considered observable. A combinational test pattern generator determines the detectability of single faults in the right-most block. The second theorem, called the multifault theorem, uses the array model with a multifault consisting of a single fault in every block. The theorem states that an untestable multifault in the array corresponds to an untestable single fault in the sequential circuit. For the array with a single block both theorems identify combinational redundancies. Experiments on ISCAS benchmarks show that using a small array size (typically, two to four blocks) we can identify a large number of sequentially untestable faults. >

A transconductor-based field-programmable analog array

Abstract: Field-programmable gate arrays for prototyping digital circuits are a widely endorsed approach for reducing time-to-market. Offering similar advantages, a field-programmable analog array (FPAA) for prototyping continuous-time analog circuits is reported here. Conceptually, a FPAA consists of configurable analog blocks (CABs) and interconnects. The function of each CAB and the connections among CABs are determined by the contents of an on-chip shift register. Different circuits can be instantiated using a FPAA by loading in different configuration bits. This IC strategy offers simplified analog circuit design with the advantages of instant prototyping, programmable topology, programmable parameters, CAD compatibility, and testability.

An implicit enumeration algorithm to generate tests for combinational logic circuits

Abstract: The D-Algorithm (DALG) is shown to be ineffective for t he class of combinational logic circuits that is used to implement Error Correction and Translation (ECAT) functions. PODEM (Path-Oriented D ecision Making) is a new test generation algorithm for combinational logic circuits. PODEM uses an implicit enumeration approach analogous to that used for solving 0 - 1 integer programming problems. It is shown that PODEM is very efficient for ECAT circuits and is significantly more efficient than DALC over the general spectrum of combinational logic circuits. its simplicity when compared to the D-Algorithm. PODEM is a complete algorithm in that it will generate a test if one exists. H euristics are used to achieve an efficient implicit search of the space of all possible primary input patterns until either a test is found or the space is exhausted. A distinctive feature of PODEM is

Fundamentals of electrical engineering

Abstract: PART I: CIRCUITS 1 Basic Elements and Laws 11 Voltage Sources, Current Sources, and Resistors 12 Kirchhoff's Current Law (KCL) 13 Kirchhoff's Voltage Law (KVL) 14 Independent and Dependent Souces 15 Instantaneous Power 2 Circuit Analysis Principles 21 Nodal Analysis 22 Determinants and Cramer's Rule 23 Mesh Analysis 24 Ideal Amplifiers 25 Thevevnin's and Norton's Theorems 26 Linearity and Superposition 3 Time-Domain Circuit Analysis 31 Inductors and Capacitors 32 Integral Relationships for Inductors and Capacitors 33 First-Order Circuits - The Natural Response 34 First-Order Circuits - The Complete Response 35 Second-Order Circuits - The Natural Response 36 Second-Order Circuits - The Complete Response 4 AC Analysis 41 Time-Domain Analysis 42 Complex Numbers 43 Frequency-Domain Analysis 44 Power 45 Important Power Concepts 46 Polyphase Circuits 47 Three-Phase Loads 5 Important Circuit and System Concepts 51 Frequency Response 52 Resonance 53 Complex Frequency 54 Introduction to Systems 55 The Laplace Transform 56 Inverse Laplace Transforms 57 Application of the Laplace Transform PART II: ELECTRONICS 6 Diodes 61 Semiconductors 62 Doped Semiconductors 63 The Junction Diode 64 The Ideal Diode 65 Nonideal-Diode Models 66 Zener Diodes 67 Effects of Capacitance 7 Bipolar Junction Transistors (BJTs) 7,1 The pnp Transistor 72 The npn Transistor 73 Cutoff and Saturation 74 Applications to Digitial Logic Circuits 75 DTL Integrated-Circuit (IC) Logic 76 Transistor-Transistor Logic (TTL) 77 Other IC Logic Families 8 Field-Effect Transistors (FETs) 81 The Junction Field-Effect Transistor (JFET) 82 Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) 83 MOSFET Logic Gates 8,4 Complementary MOSFETs (CMOS) 9 Transistor Amplifiers 91 BJT Amplifiers 92 FET Amplifiers 93 Frequency Response 94 Power Amplifiers 10 Electronic Circuits and Amplifiers 101 IC Amplifiers 102 Operational Amplifiers 103 Feedback 104 Sinusoidal Oscillators 105 Comparators 106 Introduction to Communication PART III: DIGITAL SYSTEMS 11 Digital Logic 111 Binary Numbers 112 Binary Arithmetic 113 Digital Logic Circuits 114 Boolean Algebra 115 Standard Forms of Boolean Functions 116 Simplification of Boolean Functions 12 Logic Design 121 Combinatorial Logic 122 MSI and LSI Design 123 Sequential Logic 13 Digital Devices 131 Counters 132 Registers 133 Memories 134 Digital Information Processing PART IV: ELECTROMAGNETICS 14 Electromagnetics 141 Magnetic Fields 142 Magnetic Circuits 143 Transformers 144 The Ideal Tranformer 145 Nonideal-Transformer Models 15 Machines 151 Tranducers 152 Moving-Coil and Moving-Iron Devices 153 Rotating-Coil Devices 154 Generators 155 Motors PART V: SPICE 16 SPICE 161 PSPICE 162 Transient Analysis 163 AC Analysis 164 Diodes 165 Dipolar Junction Transistors (BJTs) 166 Field-Effect Transistors (FETs) 167 Transistor Amplifiers 168 Operational Amplifiers

Techniques for reducing switching noise in high speed digital systems

Abstract: Simultaneous switching noise (SSN) caused by parasitic inductance in the power supply distribution network is a severe problem in high speed digital circuits and systems. The influence of SSN, negligible when rise/fall time is long (>5 ns), becomes an important factor, limiting circuit performance in the sub-nanosecond rise time region. This paper presents simulation results of SSN in high speed digital systems. Technical solutions for reducing SSN in the light of current developments of advanced packaging and assembly technologies are discussed. A quantitative comparison of SSN in digital systems implemented with conventional as well as advanced assembly techniques is given.

Measurement of digital circuit simulation test coverage utilizing BDDs and state bins

Abstract: Measurement of the test coverage of digital simulation of electronic circuitry is obtained (54). A Composite Circuit Model (60) has two parts: a Target Circuit Model (64) and an Environment Circuit Model (62). The Environment Circuit Model (62) models the behavior of inputs to the Target Circuit (64). The Composite Circuit Model (60) is translated into implicit FSM representations utilizing BDDs. A State Bin Transition Relation is formed which represents allowable transitions among user-specified sets of states or State Bins, and a representation of the reachable State Bins is built (94). A comparison is made (102) between data accumulated over one or more simulations (40) of the Target Circuit (64) and the data contained in the State Bin Transition Relation and the representation of the reachable State Bins. Output (52) is then generated showing which sets of circuit states were and weren't visited and which transitions allowed by the State Bin Transition Relation were and weren't taken during the simulations.

Extracting accurate and efficient timing models of latch-based designs

Abstract: A method and an apparatus for constructing a model of a digital circuit which contains level sensitive latches. The model allows for time borrowing amongst latches. Chains of latches or latch paths are collapsed together. The resulting model can be used for simulation or synthesis.

Exploiting multicycle false paths in the performance optimization of sequential logic circuits

Abstract: This paper addresses the performance optimization problem for sequential logic circuits. It is shown how the notion of false paths, traditionally defined for combinational logic circuits, can be extended to the sequential context by considering the operation of the circuit over multiple clock-cycles. These multicycle false paths can be removed from the circuit using techniques similar to those proposed for combinational logic circuits. This observation offers new techniques to improve the performance of sequential logic circuits. An implementation of an algorithm that uses these ideas shows significant performance improvement on some typical benchmark circuits at a modest area overhead. >

Substrate-aware mixed-signal macrocell placement in WRIGHT

Abstract: We describe a set of placement algorithms for handling substrate coupled switching noise. A typical mixed-signal IC has both sensitive analog and noisy digital circuits, and the common substrate parasitically couples digital switching transients into the sensitive analog regions of the chip. To preserve the integrity of sensitive analog signals, it is thus necessary to electrically isolate the analog and digital. We argue that optimal area utilization requires such isolation be designed into the system during first-cut chip-level placement. We present algorithms that incorporate commonly used isolation techniques within an automatic placement framework. Our substrate-noise evaluation mechanism uses a simplified substrate model and simple electrical representations for the noisy digital macrocells. The digital/analog interactions determined through these models are incorporated into a simulated annealing macrocell placement framework. Automatic placement results indicate these substrate-aware algorithms allow efficient mixed-signal placement optimization. >

Efficient calculation of spectral coefficients and their applications

Abstract: Spectral methods for analysis and design of digital logic circuits have been proposed and developed for several years. The widespread use of these techniques has suffered due to the associated computational complexity. This paper presents a new approach for the computation of spectral coefficients with polynomial complexity. Usually, the computation of the spectral coefficients involves the evaluation of inner products of vectors of exponential length. In the new approach, it is not necessary to compute inner products, rather, each spectral coefficient is expressed in terms of a measure of correlation between two Boolean functions. This formulation coupled with compact BDD representations of the functions reduces the overall complexity. Further, some computer aided design applications are presented that can make use of the new spectrum evaluation approach. In particular, the basis for a synthesis method that allows spectral coefficients to be computed in an iterative manner is outlined. The proposed synthesis approach has the advantage that it can accommodate a wide variety of constituent gates, including XOR gates, and complex subfunctions for realizing the circuits. >

A hybrid analog and digital VLSI neural network for intracardiac morphology classification

Abstract: Current Implantable Cardioverter Defibrillators (ICD's) use timing based decision trees for cardiac arrhythmia classification. Timing alone does not distinguish all rhythms for all patients. Hence, more computationally intensive morphology analysis is required for complete diagnosis. An analog VLSI neural network has been designed and tested to perform cardiac morphology classification tasks. Analog techniques were chosen to meet the strict power and area requirements of the implantable system while incurring the design difficulties of noise, drift and offsets inherent in analog approaches. The robustness of the neural network architecture however, to a large extent, overcomes these inherent shortcomings of the analog approach. The network is a 10:6:3 multilayer perceptron with on chip digital weight storage. The chip also includes a bucket brigade input to feed the Intracardiac Electrogram (ICEG) to the network and a Winner Take All circuit for converting classifications to a binary representation. The training system trained the network in loop and included a commercial implantable defibrillator in the signal processing path. The system has successfully distinguished two arrhythmia classes on a morphological basis for seven different patients with an average of 95% true positive and 97% true negative detections for the dangerous rhythm. The chip was implemented in 1.2 /spl mu/m CMOS and consumes less than 200 nW maximum average power from a 3 V supply in an area of 2.2/spl times/2.2 mm/sup 2/. >

General Decomposition and Its Use in Digital Circuit Synthesis

Abstract: Modem microelectronic technology.gives opportunities to build digital circuits of huge complexity and provides a wide diversity of logic building blocks. Although logic designers have been building circuits for many years, they have realized that advances in microelectronic technology are outstripping their abilities to make use of the created opportunities. In this paper, we present the fundamentals of a logic design methodology which meets the requirements of today's complex circuits and modem building blocks. The methodology is based on the theory of general full-decompositions which constitutes the theory of digital circuit structures at the highest abstraction level. The paper explains the theory and shows how it can be used for digital circuit synthesis. The decomposition methodology that is presented ensures “correctness by construction” and enables very effective and efficient post-factum validation. It makes possible extensive examination of the structural features of the required information processing in relation to a given set of objectives and constraints.

Process monitor for CMOS integrated circuits

Abstract: A process for evaluating acceptability of a digital circuit having a first type of circuit element for a first change of state and a second type of circuit element for a second change of state, the process comprising: generating a leading edge of a first pulse with a pulse generation circuit formed on a substrate in common with the digital circuit and having elements of the first and the second type; generating a trailing edge of a first pulse with a pulse generation circuit formed on a substrate in common with the digital circuit and having elements of the first and the second type; generating an accepted-rejected signal, functionally related to the width of the pulse.

LOT: logic optimization with testability—new transformations using recursive learning

Abstract: A new approach to optimize multi-level logic circuits is introduced. Given a multi-level circuit, the synthesis method optimizes its area, simultaneously enhancing its random pattern testability. The method is based on structural transformations at the gate level. New transformations involving EX-OR gates derived based on indirect implications by Recursive Learning have been introduced in the synthesis of multi-level circuits. This method is augmented with transformations that specifically enhance random-pattern testability while reducing the area. Testability enhancement is an integral part of our synthesis methodology. Experimental results show that the proposed methodology can not only realize lower area, but also achieves better testability compared to testability enhancement synthesis tools such as tstfx. Specifically for ISCAS-85 benchmark circuits, it was observed that EX-OR gate-based transformations can yield smaller circuits compared to state-of-the-art logic optimization tools like SIS and HANNIBAL.

A realistic defect oriented testability methodology for analog circuits

Abstract: Owing to the non-binary nature of their operation, analog circuits are influenced by process defects in a different manner compared to digital circuits. This calls for a careful investigation into the occurrence of defects in analog circuits, their modeling related aspects and their detection strategies. In this article, we demonstrate with the help of a real CMOS circuit that simple test stimuli, like DC, transient and AC, can detect most of the modeled process defects. Silicon devices tested with the proposed test methodology demonstrate the effectiveness of the method. Subsequently, the proposed test method is implemented in production test environment along with the conventional test for a comparative study. This test methodology is structured and simpler, therefore results in substantial test cost reduction.

Computer Circuits Electrical Design

Abstract: 1. Passive Device Modeling. 2. Circuit Simulation with SPICE. 3. System Noise Margin. 4. Digital Chip and Board Technologies. 5. Transmission Line Basics. 6. Signal Reflection Noise and Termination Schemes. 7. Crosstalk Noise. 8. Simultaneous Switching Noise. 9. Timing Analysis in Digital Circuits. 10. The Coaxial Cable. 11. Cooling and Reliability. 12. Electrical Design Processes.

Interface between programmable electronically commutated motor and personal computer and method of operation

Abstract: A microcontroller with external memory interacts with a host computer or terminal via a fully isolated RS232 serial interface. An eight-bit D/A converter transforms signals generated digitally in the microcontroller. The low level analog signal at the D/A output is further amplified in a power amplifier which supplies a signal to the motor terminals of the motor to be programmed via solid state relays. The solid state relays form an array of switches which are selectively closed by a low level digit signal generated by the microcontroller and processed by digital circuits. Four signals may be modulated with a signal representing the line frequency and are used specifically in an emulation mode. The interface receives multi-function feedback signals (RPM) from the motor such as speed, memory, content, and diagnostic information. Comparators provide an integrity check of the connections (cable) and the input section of the motor (optocouplers). The comparators compare voltages and currents of a selected motor signal against pre-defined threshold levels.

Defect-oriented test methodology for complex mixed-signal circuits

Abstract: Testing of analog blocks in digital circuits is emerging as a critical factor in the success of mixed-signal ICs. The present specification-oriented testing of these blocks results in high test costs and doesn't ensure detection of all defects, causing potential reliability problems. To solve these problems, in this paper a defect-oriented test methodology for mixed analog-digital circuits is proposed. The strength of the method is demonstrated by an implementation for a complex mixed-signal circuit, a flash analog-to-digital converter. It is shown that with simple tests 93% of the defects in this circuit can be detected. Moreover application of DfT guidelines derived from this test methodology may improve the defect coverage to 99%. First impressions lead to the conclusion that the analyzed test obtains a higher defect coverage with lower test costs than functional tests. >

Dynamic characteristics of inverter circuits using single electron transistors

Abstract: We have investigated the basic characteristics of capacitively and resistively coupled single-electron tunneling (SET) inverters as a digital logic circuit Static and dynamic characteristics have been calculated based on the semiclassical model using the Monte Carlo method Although a voltage gain larger than unity is found even in a cascade connection of two stages of the SET inverters, they reveal some disadvantages in digital logic application, such as small voltage gain, poor input-output separation, small logic level difference, instability of operating point and oscillating output voltages The switching delay time is estimated to be on the order of 100RC, where R and C is resistance and capacitance of a tunnel junction, respectively The stability of logic voltage levels has also been verified in cross-coupled latch circuits

Resonant tunneling transistor and its application to multiple-valued logic circuits

Abstract: Progress in multiple-valued logic (MVL) depends much on the development of devices that are inherently suitable for MVL operation. With their multiple stable states, resonant tunneling devices are promising candidates. Although not at a matured stage yet, resonant tunneling transistors (RTTs) and diodes (RTDs) are expected to be indispensable for practical applications of MVL in the near future. In this paper, state-of-the-art RTT technology is reviewed with some issues to be addressed. Possible applications are also discussed in terms of coupled-quantum-well base RTTs and monostable-multistable logic circuits.

On the prediction of digital circuit susceptibility to radiated EMI

Abstract: The effects of radiated radio-frequency interference (RFI) on the operation of digital systems are studied by simulating the response of simple logic circuits to incident plane waves. The simulation is accomplished by combining a linear electromagnetic moment-method model of the wire structure with a nonlinear circuit model of the solid-state components. The complete model is analyzed in the linear and nonlinear regimes as an example. It is shown how a circuit simulator, such as SPICE, can be used in the analysis of an arbitrary wire network loaded with logic circuits, by the process of representing the linear wire network as a lumped-element N-port /spl pi/ network and interfacing it to the nonlinear circuit simulator. Examples are given that demonstrate the occurrence of both static and dynamic failures under various RFI-field excitations and wire structure geometries. The prediction methods presented in this paper, can be used by EMC engineers to assess the likelihood of failures in RFI-exposed digital systems,.

Positive feedback circuit for fast domino logic

Abstract: A logic circuit is described. The logic circuit generates a first signal state in response to a first set of input signals, generates a second signal state in response to a second set of input signals, activates a bypass switch in response to the first signal state, and bypasses a domino logic unit in response to the first signal state.