Showing papers on "Digital electronics published in 2000"

Dual-threshold voltage techniques for low-power digital circuits

Abstract: Scaling and power reduction trends in future technologies will cause subthreshold leakage currents to become an increasingly large component of total power dissipation This paper presents several dual-threshold voltage techniques for reducing standby power dissipation while still maintaining high performance in static and dynamic combinational logic blocks MTCMOS sleep transistor sizing issues are addressed, and a hierarchical sizing methodology based on mutual exclusive discharge patterns is presented A dual-V/sub t/ domino logic style that provides the performance equivalent of a purely low-V/sub t/ design with the standby leakage characteristic of a purely high-V/sub t/ implementation is also proposed

The VLSI handbook

Abstract: VLSI TECHNOLOGY Bipolar Technology B. Gunnar Malm, Jan V. Grahn and Mikael Ostling CMOS/BiCMOS Technology Yasuhiro Katsumata, Tatsuya Ohguro, Kazumi Inoh, Eiji Morifuji, Takashi Yoshitomi, Hideki Kimijima, Hideaki Nii, Toyota Morimoto, Hisayo S. Momose, Kuniyoshi Yoshikawa, Hidemi Ishiuchi and Hiroshi Iwai Silicon-On-Insulator Technology Sorin Cristoloveanu SiGe HBT Technology John D. Cressler Silicon Carbide Technology Philip G. Neudeck Passive Components Ashraf Lotfi Power IC Technologies Akio Nakagawa Microelectronics Packaging Bi-Shiou Chiou Multichip Module Technologies Victor Boyadzhyan and John Choma, Jr. DEVICES AND THEIR MODELS Bipolar Junction Transistor Circuits David J. Comer and Donald T. Comer RF Passive IC Components Thomas H. Lee, Maria del Mar Hershenson, Sunderarajan S. Mohan, Kirad Samavati and C. Patrick Yue CMOS Fabrication Jeff Jessing Analog Circuit Simulation J. Gregory Rollins Interconnect Modeling and Simulation Michel S. Nakhla and Ramachandra Achar LOW POWER ELECTRONICS AND DESIGN System-Level Power Management: An Overview Ali Iranli and Massoud Pedram Communication-Based Design for Nanoscale SoCs Umit Y. Ogras and Radu Marculescu Power-Aware Architectural Synthesis Robert P. Dick, Li Shang and Niraj K. Jha Dynamic Voltage Scaling for Low-Power Hard Real-Time Systems Jihong Kim, Flavius Gruian and Dongkun Shin Low-Power Microarchitecture Techniques and Compiler Design Techniques Emil Talpes and Diana Marculescu Architecture and Design Flow Optimizations for Power-Aware FPGAs Aman Gayasen and Narayanan Vijaykrishnan Technology Scaling and Low-Power Circuit Design Ali Keshavarzi AMPLIFIERS CMOS Amplifier Design Harry W. Li, R. Jacob Baker and Donald C. Thelen Bipolar Junction Transistor Amplifiers David J. Comer and Donald T. Comer High-Frequency Amplifiers Chris Toumazou and Alison Burdett Operational Transconductance Amplifiers Mohammed Ismail, Seok-Bae Park, Ayman A. Fayed and R.F. Wassenaar LOGIC CIRCUITS Expressions of Logic Functions Saburo Muroga Basic Theory of Logic Functions Saburo Muroga Simplification of Logic Expressions Saburo Muroga Binary Decision Diagrams Shin-ichi Minato and Saburo Muroga Logic Synthesis with AND and OR Gates in Two Levels Saburo Muroga Sequential Networks Saburo Muroga Logic Synthesis with AND and OR Gates in Multi-Levels Yuichi Nakamura and Saburo Muroga Logic Properties of Transistor Circuits Saburo Muroga Logic Synthesis with NAND (or NOR) Gates in Multi-Levels Saburo Muroga Logic Synthesis with a Minimum Number of Negative Gates Saburo Muroga Logic Synthesizer with Optimizations in Two Phases Ko Yoshikawa and Saburo Muroga Logic Synthesizer by the Transduction Method Saburo Muroga Emitter-Coupled Logic Saburo Muroga CMOS Saburo Muroga Pass Transistors Kazuo Yano and Saburo Muroga Adders Naofumi Takagi, Haruyuki Tago, Charles R. Baugh and Saburo Muroga Multipliers Naofumi Takagi, Charles R. Baugh and Saburo Muroga Dividers Naofumi Takagi and Saburo Muroga Full-Custom and Semi-Custom Design Saburo Muroga Programmable Logic Devices Saburo Muroga Gate Arrays Saburo Muroga Field-Programmable Gate Arrays Saburo Muroga Cell-Library Design Approach Saburo Muroga Comparison of Different Design Approaches Saburo Muroga MEMORY, REGISTERS AND SYSTEM TIMING System Timing Baris Taskin, Ivan S. Kourtev and Eby G. Friedman ROM/PROM/EPROM Jen-Sheng Hwang SRAM Yuh-Kuang Tseng Embedded Memory Chung-Yu Wu Flash Memories Rick Shih-Jye Shen, Frank Ruei-Ling Lin, Amy Hsiu-Fen Chou, Evans Ching-Song Yang and Charles Ching-Hsiang Hsu Dynamic Random Access Memory Kuo-Hsing Cheng Content-Addressable Memory Chi-Sheng Lin and Bin-Da Liu Low-Power Memory Circuits Martin Margala ANALOG CIRCUITS Nyquist-Rate ADC and DAC Bang-Sup Song Oversampled Analog-to-Digital and Digital-to-Analog Converters John W. Fattaruso and Louis A. Williams III RF Communication Circuits Michiel Steyaert, Wouter De Cock and Patrick Reynaert PLL Circuits Muh-Tian Shiue and Chorng-kuang Wang Switched-Capacitor Filters Andrea Baschirotto MICROPROCESSOR AND ASIC Timing and Signal Integrity Analysis Abhijit Dharchoudhury, David Blaauw and Shantanu Ganguly Microprocessor Design Verification Vikram Iyengar Microprocessor Layout Method Tanay Karnik Architecture Daniel A. Connors and Wen-mei W. Hwu Logic Synthesis for Field Programmable Gate Array (FPGA) Technology John Lockwood TESTING OF DIGITAL SYSTEMS Design for Testability and Test Architectures Dimitri Kagaris, Nick Kanopoulos and Spyros Tragoudas Automatic Test Pattern Generation Spyros Tragoudas Built-In Self Test Dimitri Kagaris COMPOUND SEMICONDUCTOR INTEGRATED CIRCUIT TECHNOLOGY Compound Semiconductor Materials Stephen I. Long Compound Semiconductor Devices for Analog and Digital Circuits Donald B. Estreich Compound Semiconductor RF Circuits Donald B. Estreich High-Speed Circuit Design Principles Stephen I. Long DESIGN AUTOMATION Internet-Based Micro-Electronic Design Automation (IMEDA) Framework Moon Jung Chung and Heechul Kim System-Level Design Alice C. Parker, Yosef Tirat-Gefen and Suhrid A. Wadekar Performance Modeling and Analysis Using VHDL and SystemC Robert H. Klenke, Jonathan A. Andrews and James H. Aylor Embedded Computing Systems and Hardware/Software Co-Design Wayne Wolf Design Automation Technology Roadmap Donald R. Cottrell VLSI SIGNAL PROCESSING Computer Arithmetic for VLSI Signal Processing Earl E. Swartzlander Jr. VLSI Architectures for JPEG 2000 EBCOT: Design Techniques and Challenges Yijun Li and Magdy Bayoumi VLSI Architectures for Forward Error-Control Decoders Arshad Ahmed, Seok-Jun Lee, Mohammad Mansour and Naresh R. Shanbhag An Exploration of Hardware Architectures for Face Detection T. Theocharides, C. Nicopoulos, K. Irick, N. Vijaykrishnan and M.J. Irwin Multidimensional Logarithmic Number System Roberto Muscedere, Vassil S. Dimitrov and Graham A. Jullien DESIGN LANGUAGES Languages for Design and Implementation of Hardware Zainalabedin Navabi System Level Design Languages Shahrzad Mirkhani and Zainalabedin Navabi RT Level Hardware Description with VHDL Mahsan Rofouei and Zainalabedin Navabi Register Transfer Level Hardware Description with Verilog Zainalabedin Navabi Register-Transfer Level Hardware Description with SystemC Shahrzad Mirkhani and Zainalabedin Navabi System Verilog Saeed Safari VHDL-AMS Hardware Description Language Naghmeh Karimi and Zainalabedin Navabi Verification Languages Hamid Shojaei and Zainalabedin Navabi ASIC and Custom IC Cell Information Representation Naghmeh Karimi and Zainalabedin Navabi Test Languages Shahrzad Mirkhani and Zainalabedin Navabi Timing Description Languages Naghmeh Karimi and Zainalabedin Navabi HDL-Based Tools and Environments Saeed Safari Index

POIROT: a logic fault diagnosis tool and its applications

Abstract: Logic fault diagnosis or fault isolation is the process of analyzing the failing logic portions of an integrated circuit to isolate the cause of failure. Fault diagnosis plays an important role in multiple applications at different stages of design and manufacturing. A logic diagnosis tool with applicability to a spectrum of logic DFT, ATPG and test strategies including full/almost fullscan circuits with combinational ATPG, partial-scan and non-scan circuits with sequential ATPG and to functional patterns in general is presented. Novel features incorporated into the tool include static and dynamic structural processing for partial-scan circuits, windowed fault simulation, and diagnostic models for open defects and cover algorithms for multiple fault diagnosis. Experimental results include simulation results on processor functional blocks and silicon results on chipsets and processors from artificially induced defects and production fallout.

Fault-tolerant evolvable hardware using field-programmable transistor arrays

Abstract: The paper presents an evolutionary approach to the design of fault-tolerant VLSI (very large scale integrated) circuits using EHW (evolvable hardware). The EHW research area comprises a set of applications where GA (genetic algorithms) are used for the automatic synthesis and adaptation of electronic circuits. EHW is particularly suitable for applications requiring changes in task requirements and in the environment or faults, through its ability to reconfigure the hardware structure dynamically and autonomously. This capacity for adaptation is achieved via the use of GA search techniques, in our experiments, a fine-grained CMOS (complementary metal-oxide silicon) FPTA (field-programmable FPGA transistor array) architecture is used to synthesize electronic circuits. The FPTA is a reconfigurable architecture, programmable at the transistor level and specifically designed for EHW applications. The paper demonstrates the power of EA to design analog and digital fault-tolerant circuits. It compares two methods to achieve fault-tolerant design, one based on fitness definition and the other based on population. The fitness approach defines, explicitly, the faults that the component can encounter during its life, and evaluates the average behavior of the individuals. The population approach, on the other hand, uses the implicit information of the population statistics accumulated by the GA over many generations. The paper presents experiment results obtained using both approaches for the synthesis of a fault-tolerant digital circuit (XNOR) and a fault-tolerant analog circuit (multiplier).

A digital CMOS design technique for SEU hardening

Abstract: A new cell design technique is described which may be used to create SEU hardened circuits. The technique uses actively biased, isolated well transistors to prevent transients in combinational logic from reaching the output node.

Towards the automatic design of more efficient digital circuits

Abstract: This paper introduces a new methodology of evolving electronic circuits by which the process of evolutionary design is guaranteed to produce a functionally correct solution. The method employs a mapping to represent an electronic circuit on an array of logic cells that is further encoded within a genotype. The mapping is many-to-one and thus there are many genotypes that have equal fitness values. Genotypes with equal fitness values define subgraphs in the resulting fitness landscapes referred to as neutral networks. This is further used in the design of a neutral network that connects the conventional with other more efficient designs. To explore such a network a navigation strategy is defined by which the space of all functionally correct circuits can be explored. The paper shows that very efficient digital circuits can be obtained by evolving from the conventional designs. Results for several binary multiplier circuits such as the three and four-bit multipliers are reported. The evolved solution for the three-bit multiplier consists of 23 two-input logic gates that in terms of number of two-input gates used is 23.3% more efficient than the most efficient known conventional design. The logic operators required to implement this circuit are 14 ANDs, 9 XORs, and 2 inversions (NOT). The evolved four-bit multiplier consists of 57 two-input logic gates that is 10.9% more efficient (in terms of number of two-input gates used) than the most efficient known conventional design. The optimal size of the target circuits is also studied by measuring the length of the neutral walks from the obtained designs.

Clock skew verification in the presence of IR-drop in the power distribution network

Abstract: Clocks are perhaps the most important circuits in high-speed digital systems. The design of clock circuitry and the quality of clock signals directly impact the performance of a very large scale integrated chip. Clock skew verification requires high accuracy and is typically performed using circuit simulators. However in high-performance deep-submicrometer digital circuits, clocks are running at higher frequencies and are driving more gates than ever, thus presenting a higher current load on the power distribution network with the potential for substantial power grid voltage (IR)-drop. This IR-drop affects the clock timing and must be taken into account in the verification process. Since IR-drop is a full-chip phenomenon, the use of standard circuit simulation on both the clock circuitry and the power-grid is not practical. In this paper, we present a new methodology for the verification of clock delay and skew. An iterative technique is presented for clock simulation in the presence of full-chip dynamic IR-drop. The effect of IR-drop on the timing of clock signals is quantified on a small example, and demonstrated on a large chip.

BDS: a BDD-based logic optimization system

Abstract: This paper describes a new BDD-based logic optimization system, BDS. It is based on a recently developed theory for BDD-based logic decomposition, which supports both algebraic and Boolean factorization. New techniques, which are crucial to the manipulation of BDDs in a partitioned Boolean network environment, are described in detail. The experimental results show that BDS has a capability to handle very large circuits. It offers a superior runtime advantage over SIS, with comparable results in terms of circuit area and often improved delay.

Scalability problems of digital circuit evolution evolvability and efficient designs

Abstract: A major problem in the evolutionary design of combinational circuits is the problem of scale. This refers to the design of electronic circuits in which the number of gates required to implement the optimal circuit is too high to search the space of all designs in reasonable time, even by evolution. The reason is twofold: firstly, the size of the search space becomes enormous as the number of gates required to implement the circuit is increased, and secondly, the time required to calculate the fitness of a circuit grows as the size of the truth table of the circuit. This paper studies the evolutionary design of combinational circuits, particularly the three-bit multiplier circuit, in which the basic building blocks are small sub-circuits, modules inferred from other evolved designs. The structure of the resulting fitness landscapes is studied and it is shown that in general the principles of evolving digital circuits are scalable. Thus to evolve digital circuits using modules is faster, since the building blocks of the circuit are sub-circuits rather than two-input gates. This can also be a disadvantage, since the number of gates of the evolved designs grows as the size of the modules used.

Analysis of single-event effects in combinational logic-simulation of the AM2901 bitslice processor

Abstract: Using SEUTool (a synthesized VHDL based simulator of single-event fault propagation in combinational circuitry), we have performed a single-event study on a custom-designed CMOS AM2901, a 4-bit bit-slice processor. Analysis shows interesting general trends for single-event upset effects in complex combinational/sequential circuits.

Speed and area tradeoffs in cluster-based FPGA architectures

Abstract: One way to reduce the delay and area of field-programmable gate arrays (FPGAs) is to employ logic-cluster-based architectures, where a logic cluster is a group of logic elements connected with high-speed local interconnections. In this paper, we empirically evaluate FPGA architectures with logic clusters ranging in size from 1 to 20, and show that compared to architectures with size 1 clusters, architectures with size 8 clusters have 23% less delay (30% faster clock speed) and require 14% less area. We also show that FPGA architectures with large cluster sizes can significantly reduce design compile time-an increasingly important concern as the logic capacity of FPGA's rises. For example, an architecture that uses size 20 clusters requires seven times less compile time than an architecture with size 1 clusters.

Impact of systematic spatial intra-chip gate length variability on performance of high-speed digital circuits

Abstract: Using data collected from an actual state-of-the-art fabrication facility, we conducted a comprehensive characterization of an advanced 0.18 /spl mu/m CMOS process. The measured data revealed significant systematic, rather than random, spatial intra-chip variability of MOS gate length, leading to large circuit path delay variation. The critical path value of a combinational logic block varies by as much as 17%, and the global skew is increased by 8%. Thus, a significant timing error (/spl sim/25%) and performance loss takes place if variability is not properly addressed. We derive a model, which allows estimating performance degradation for the given circuit and process parameters. Analysis shows that the spatial, rather than proximity-dependent, systematic Lgate variability is the main cause of large circuit speed degradation. The degradation is worse for the circuits with a larger number of critical paths and shorter average logic depth. We propose a location-dependent timing analysis methodology that allows to mitigate the detrimental effects of Lgate variability, and developed a tool linking the layout-dependent spatial information to circuit analysis. We discuss the details of the practical implementation of the methodology, and provide the guidelines for managing the design complexity.

Generating synthetic benchmark circuits for evaluating CAD tools

Abstract: For the development and evaluation of computer-aided design tools for partitioning, floorplanning, placement, and routing of digital circuits, a huge amount of benchmark circuits with suitable characteristic parameters is required. Observing the lack of industrial benchmark circuits available for use in evaluation tools, one could consider to actually generate synthetic circuits. In this paper, we extend a graph-based benchmark generation method to include functional information. The use of a user-specified component library, together with the restriction that no combinational loops are introduced, now broadens the scope to timing-driven and logic optimizer applications. Experiments show that the resemblance between the characteristic Rent curve and the net degree distribution of real versus synthetic benchmark circuits is hardly influenced by the suggested extensions and that the resulting circuits are more realistic than before. An indirect validation verifies that existing partitioning programs have comparable behavior for both real and synthetic circuits. The problems of accounting for timing-aware characteristics in synthetic benchmarks are addressed in detail and suggestions for extensions are included.

High-level simulation of substrate noise generation including power supply noise coupling

Abstract: Substrate noise caused by large digital circuits will degrade the performance of analog circuits located on the same substrate. To simulate this performance degradation, the total amount of generated substrate noise must be known. Simulating substrate noise generated by large digital circuits is however not feasible with existing circuit simulators and detailed substrate models due to the long simulation times and high memory requirements. We have developed a methodology to simulate this substrate noise generation at a higher level. Not only does this methodology take noise coupling from switching gates into account, but also noise coupling from the power supply is included. This paper describes this simulation methodology. In the paper it is shown that the high-level simulations correspond very well with SPICE simulations and that a large gain in simulation speed is obtained. This high-level simulation methodology makes it possible to predict substrate noise generation of large digital circuits in a very efficient way, early in the design flow of mixed-signal ASICs.

Glitch power minimization by selective gate freezing

Abstract: This paper presents a technique for glitch power minimization in combinational circuits. The total number of glitches is reduced by replacing some existing gates with functionally equivalent ones (called F-Gates) that can be "frozen" by asserting a control signal. A frozen gate cannot propagate glitches to its output. Algorithms for gate selection and clustering that maximize the percentage of filtered glitches and reduce the overhead for generating the control signals are introduced. A power-efficient CMOS implementation of F-Gates is also described. An important feature of the proposed method is that it can be applied in place directly to layout-level descriptions; therefore, it guarantees very predictable results and minimizes the impact of the transformation on circuit size and speed.

Improved global rational approximation macromodeling algorithm for networks characterized by frequency-sampled data

Abstract: Recently, the demand for high-performance wireless designs has been increasing while simultaneously the speed of high-end digital designs have crossed over the gigahertz range. New simulation tools which accurately characterize high-frequency interconnects are needed. This paper presents improvements to a new macromodeling algorithm. The algorithm employs curve-fitting techniques to achieve a pole-residue approximation of the frequency-sampled network. The frequency sampled S-parameters or Y-parameters can be obtained from measurement or full-wave simulation to characterize the frequency-dependent interconnects behavior. The improvements extend the approach to lossless structures, increase its accuracy with pole-clustering, and ensure its validity with a passivity test. This paper addresses some of the special considerations that must be made to the method so it can efficiently and accurately be applied to lossless circuits and structures. The resulting algorithm is now capable of accurately extracting a wide-band frequency domain macromodel from frequency-sampled data for either LC circuit (lossless) or RLC circuits (lossy). The frequency-domain macromodel can be linked to a SPICE circuit simulator for mixed signal circuit analysis using RF, analog, and digital circuits. The circuit can be simulated in the time domain using recursive convolution.

High-speed and low-power CMOS priority encoders

Abstract: The design of two high-performance priority encoders is presented. The key techniques for high speed are twofold. First, a multilevel look-ahead structure is developed to shorten the critical path effectively. Second, this look-ahead structure is realized efficiently by the NP Domino CMOS logic, and all the dynamic gates have a parallel-connected circuit structure. For high speed and low power at the same time, the series-connected circuit structure is adopted in the less critical paths to reduce the switching activity, but such a design needs to cascade two n-type dynamic gates directly resulting in the race problem. A special circuit technique is utilized to rescue this problem. Several 32-bit priority encoders are designed to evaluate the feasibility of the proposed techniques. The best new design realizes a three-level look-ahead structure, and it achieves 65% speed improvement, 20% layout area reduction, and 30% power reduction simultaneously as compared to the conventional design with a simple look-ahead structure.

IGRAINE-an Implication GRaph-bAsed engINE for fast implication, justification, and propagation

Abstract: Implication, justification, and propagation are three important Boolean problems that have to be solved during many tasks in electronic design automation (EDA) for digital circuits. As they constitute the key components of automatic test pattern generation (ATPG) most algorithms that tackle these problems originate in ATPG research. Due to their fundamental nature these ATPG-based methods have successfully been adopted by logic synthesis and formal verification where they have helped advance the fields of netlist optimization and Boolean equivalence checking. Despite their high importance and wide applicability, the data structures and algorithms suggested so far have proven to be suboptimal and inflexible in several respects. Therefore, we propose IGRAINE, a fast and flexible engine for performing implication, justification, and propagation in combinational circuits that is specifically optimized with respect to these tasks. Due to its modular design, IGRAINE is easily included into new applications that require ATPG-based methods. Our approach is based on a new implication graph (IG) model which forms the core of IGRAINE. Contrary to other IG models, the proposed IG represents all information on the implemented logic function as well as the topology of a combinational circuit in a single graph model. In order to demonstrate the performance of the presented IG-based algorithms for implication, justification, and propagation, we provide experimental results for stuck-at and path delay fault ATPG as well as Boolean equivalence checking. They show that TIP outperforms the state-of-the-art in SAT-based and structure-based ATPG. A comparison with tools for Boolean equivalence checking demonstrates the high effectiveness of our approach.

Measuring and modeling the effects of substrate noise on the LNA for a CMOS GPS receiver

Abstract: The influence of substrate noise generated in a digital circuit on the low-noise amplifier (LNA) of a CMOS GPS receiver has been experimentally characterized and theoretically analyzed. A frequency domain approach is used to model noise injection into the substrate from the digital circuitry and the mechanisms by which that noise can affect analog circuit behavior. The results reveal that substrate noise can modulate the LNA input signals as well as directly couple to the LNA output.

Complete logic family using tunneling-phase-logic devices

Abstract: This paper presents the work done to develop and characterize the behavior of binary tunneling phase logic (TPL) devices. Three input NAND, NOR and MINORITY functions are demonstrated using a single TPL element. The fan-out of the gates is discussed as well as the loading effects of multiple gates in cascade. Stable regions of operation are reported and future research possibilities are explored.

Precise test generation for resistive bridging faults of CMOS combinational circuits

Abstract: In this paper we propose a new method to detect resistive bridging faults by logic testing considering fault effects that depend on the gate threshold voltage and gate input vectors. First we show that some bridging faults can be missed to be detected by the traditional test generation method which generates O and 1 at the bridging signal lines, and then propose a novel method to detect resistive bridging faults by logic testing method, which is complete in the sense that the undetectable resistive bridging fault by this algorithm gives correct result in logical operation. A heuristic method using a random pattern has also been proposed for experimental purpose. In order to show the effectiveness of the proposed method some experimental results for benchmark circuits have been shown.

Slope propagation in static timing analysis

Abstract: Static timing analysis has traditionally used the PERT method for identifying the critical path of a digital circuit Due to the influence of the slope of a signal at a particular node on the subsequent path delay, an earlier signal with a signal slope greater than the slope of the later signal may result in a greater delay Therefore, the traditional method for timing analysis may identify the incorrect critical path and report an optimistic delay for the circuit We show that the circuit delay calculated using the traditional method is a discontinuous function with respect to transistor and gate sizes, posing a severe problem for circuit optimization methods We propose a new timing analysis algorithm which resolves both these issues The proposed algorithm selectively propagates multiple signals through each timing edge in cases where there exists ambiguity regarding which arriving signal represents the critical path The algorithm for propagating the corresponding required times is also presented We prove that the proposed algorithm identifies a circuit's true critical path, where the traditional timing analysis method may not We also show that under this method circuit delay and node slack are continuous functions with respect to a circuit's transistor and gate sizes In addition, we present a heuristic method which reduces the number of signals to be propagated at the expense of a slight loss in accuracy Finally, we show how the proposed algorithm was efficiently implemented in an industrial static timing analysis and optimization tool, and present results for a number of industrial circuits Our results show that the traditional timing analysis method underestimates the circuit delay by as much as 38%, while that the proposed method efficiently finds the correct circuit delay with only a slight increase in run time

Sequential fault modeling and test pattern generation for CMOS iterative logic arrays

Abstract: Iterative Logic Arrays (ILAs) are widely used in the datapath parts of digital circuits, like general purpose microprocessors, embedded processors, and digital signal processors. Testing strategies based on more comprehensive fault models than the traditional combinational fault models have become an imperative need in CMOS technology. In this paper, first, we introduce a comprehensive, cell-level, sequential fault model suitable for ILAs, termed Realistic Sequential Cell Fault Model (RS-CFM). RS-CFM drastically reduces test complexity compared to exhaustive two-pattern testing proposed so far in the literature for sequential ILA testing, without sacrificing test quality. In addition, it favors robustness of sequential test sets both at the cell and the array levels. Second, a new Automatic Test Pattern Generator (ILA-ATPG) based on RS-CFM for the case of one-dimensional ILAs is presented. ILA-ATPG can handle all classes of one-dimensional ILAs: unilateral or bilateral ILAs, with or without vertical inputs/outputs. Based on a graph model, ILA-ATPG explores the C-testability and linear-testability of the ILA under test and resolves the test invalidation problem constructing robust test sequences. The efficiency of ILA-ATPG is demonstrated through a comprehensive set of experimental results over all classes of one-dimensional ILAs, including all practical one-dimensional ILAs, as well as a number of more complex benchmarks.

A self-correcting active pixel camera

Abstract: Digital cameras on-a-chip are becoming more common and are expected to be used in many industrial and consumer products. With the size of the CMOS active pixel-array implemented in such chips increasing to 512/spl times/512 and beyond, the possibility of degradation in the reliability of the chip over time must be a factor in the chip design. In digital circuits, a commonly used technique for reliability or yield enhancement is the incorporation of redundancy (e.g., adding redundant rows and columns in large memory ICs). Very limited attempts have been directed towards fault-tolerance in analog circuits, mainly due to the very high level of irregularity in their design. Since active pixel arrays have a regular structure, they are amenable to reliability enhancement through a limited amount of added redundancy. The purpose of this paper is to investigate the advantages of incorporating some fault-tolerance methods, including redundancy, into the design of an active pixel sensor array.

A current driven routing and verification methodology for analog applications

Abstract: We present a new methodology for current driven routing and layout verification for analog applications used to avoid defects due to electromigration.The methodology presented uses a commercial simulator to calculate the current flow at all terminals of the analog circuit. Afterwards maximum currents per terminal are extracted and used as guidance for the Current Driven Router (CDR) which is capable of routing analog multiterminal signal nets with current driven wire widths.The Current Density Simulator (CDS) is used to compute and verify current densities in layouts that were generated using a 'standard' routing methodology.

Don't cares and multi-valued logic network minimization

Abstract: We address optimizing multi-valued (MV) logic functions in a multi-level combinational logic network. Each node in the network, called an MV-node, has multi-valued inputs and single multi-valued output. The notion of don't cares used in binary logic is generalized to multi-valued logic. It contains two types of flexibility: incomplete specification and non-determinism. We generalize the computation of observability don't cares for a multi-valued function node. Methods are given to compute (a) the maximum set of observability don't cares, and (b) the compatible set of observability don't cares for each MV-node. We give a recursive image computation to transform the don't cares into the space of local inputs of the node to be minimized. The methods are applied to some experimental multi-valued networks, and demonstrate reduction in the size of the tables that represent multi-valued logic functions.

The test vector problem and limitations to evolving digital circuits

Abstract: How do we know the correctness of an evolved circuit? While Evolutionary Hardware is exhibiting its effectiveness, we argue that it is very difficult to design a large-scale digital circuit by conventional evolutionary techniques alone, if we are using a subset of the entire truth table for fitness evaluation. The test vector generation problem for testing VLSI (Very Large Scale Integration) suggests that there is no efficient way to determine a training set which assures full correctness of an evolved circuit.

Semiconductor integrated circuit

Abstract: PROBLEM TO BE SOLVED: To verify a wiring route for connecting an analog circuit, a digital circuit and both the circuits in a hybrid semiconductor integrated circuit. SOLUTION: The hybrid semiconductor integrated circuit C0 for inputting an output signal of a digital circuit C1 to an analog circuit C2 comprises first selectors F0 to F7 for switching the signal of the circuit C1 and signals from external terminals TI0 to TI7 by a mode switching signal S0 to input it to the circuit C2, and a selector F8 for switching outputs of an analog signal processor D0 for constituting the circuit C2 and a P-s conversion block DS1 to output it to an exterior. Second external terminals TO0 to TO7 are connected to the output of the first selector. Thus, the wiring route for connecting the circuit C2 to the circuit C1 and the external terminal are selectively connected to verify an independent operation of both the circuits and the route.

A Flexible Model of a CMOS Field Programmable Transistor Array Targeted for Hardware Evolution

Abstract: This article focuses on the properties of a fine grained re-configurable transistor array currently under test at the Jet Propulsion Laboratory (JPL). This Field Programmable Transistor Array (FPTA) is integrated on a Complementary Metal-Oxide Semiconductor (CMOS) chip. The FPTA has advantageous features for hardware evolutionary experiments when compared to programmable circuits with a coarse level of granularity. Although this programmable chip is configured at a transistor level, its architecture is flexible enough to implement standard analog and digital circuits' building blocks with a higher level of complexity. This model and a first set of evolutionary experiments have been recently introduced. Here, the objective is to further illustrate its flexibility and versatility for the implementation of a variety of circuits in comparison with other models of re-configurable circuits. New evolutionary experiments are also presented, serving as a basis for the authors to devise an improved model for the FPTA, to be fabricated in the near future.

In-system programmable flash memory device with trigger circuit for generating limited duration program instruction

Abstract: A trigger circuit for an In-System Programmable (ISP) memory device that operates with a JTAG interface. The trigger circuit receives instruction signals from the JTAG control circuitry, and limits the duration of these instruction signals to avoid erroneously repeating ISP programming operations. The trigger circuit includes a first logic circuit, a delay circuit, and a second logic circuit. The first logic circuit generates a logic high output when both the JTAG RUN-TEST and a program instruction signal are simultaneously asserted, and causes the second logic circuit to toggle the limited duration instruction signal into a logic high state. The delay circuit also detects the simultaneous assertion of the JTAG RUN-TEST and a program instruction signal, and generates a cancellation signal after a predetermined number of clock cycles. The cancellation signal causes the second logic circuit to toggle the limited duration instruction signal into a logic low state.