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Showing papers on "Digital electronics published in 2004"


Proceedings ArticleDOI
13 Sep 2004
TL;DR: Logic and memory design techniques allowing subthreshold operation are developed and demonstrated and the fabricated 1024-point FFT processor operates down to 180mV using a standard 0.18/spl mu/m CMOS logic process while using 155nJ/FFT at the optimal operating point.
Abstract: Minimizing energy requires scaling supply voltages below device thresholds. Logic and memory design techniques allowing subthreshold operation are developed and demonstrated. The fabricated 1024-point FFT processor operates down to 180mV using a standard 0.18/spl mu/m CMOS logic process while using 155nJ/FFT at the optimal operating point.

270 citations


Proceedings ArticleDOI
22 Feb 2004
TL;DR: This paper extends a technique that uses on-chip jitter and PLLs to a much larger class of FPGAs that do not contain PLLing to produce random bits at speeds of up to 0.5 Mbits/second with good statistical characteristics.
Abstract: Field Programmable Gate Arrays (FPGAs) are an increasingly popular choice of platform for the implementation of cryptographic systems. Until recently, designers using FPGAs had less than optimal choices for a source of truly random bits. In this paper we extend a technique that uses on-chip jitter and PLLs to a much larger class of FPGAs that do not contain PLLs. Our design uses only the Configurable Logic Blocks (CLBs) common to all FPGAs, and has a self-testing capability. Using the intrinsic jitter contained in digital circuits, we produce random bits at speeds of up to 0.5 Mbits/second with good statistical characteristics. We discuss the engineering challenges of extracting random bits from digital circuits, and we report the results of running standard statistical tests (NIST) on the output generated by our system.

190 citations


Proceedings ArticleDOI
11 Oct 2004
TL;DR: The strong configurability of the VCGA allows us to minimize the number of fixed parts in a general-purpose VCGA fabric, which greatly improves area utilization.
Abstract: In this paper, we provide a comprehensive study of the mappability of a via-configurable gate array (VCGA). Although, the base cell of the VCGA is simple, by customizing only via masks it can implement various combinational logic functions, sequential elements, and SRAM cells. Our VCGA can be efficiently configured into SRAM arrays, adders and multipliers. The strong configurability of our VCGA allows us to minimize the number of fixed parts in a general-purpose VCGA fabric, which greatly improves area utilization.

159 citations


Journal ArticleDOI
TL;DR: It is demonstrated through analysis and simulation that using the proposed method the noise tolerance of dynamic logic gates can be improved beyond the level of static CMOS logic gates while the performance advantage of dynamic circuits is still retained.
Abstract: Dynamic CMOS logic circuits are widely employed in high-performance VLSI chips in pursuing very high system performance. However, dynamic CMOS gates are inherently less resistant to noises than static CMOS gates. With the increasing stringent noise requirement due to aggressive technology scaling, the noise tolerance of dynamic circuits has to be first improved for the overall reliable operation of VLSI chips designed using deep submicron process technology. In the literature, a number of design techniques have been proposed to enhance the noise tolerance of dynamic logic gates. An overview and classification of these techniques are first presented in this paper. Then, we introduce a novel noise-tolerant design technique using circuitry exhibiting a negative differential resistance effect. We have demonstrated through analysis and simulation that using the proposed method the noise tolerance of dynamic logic gates can be improved beyond the level of static CMOS logic gates while the performance advantage of dynamic circuits is still retained. Simulation results on large fan-in dynamic CMOS logic gates have shown that, at a supply voltage of 1.6 V, the input noise immunity level can be increased to 0.8 V for about 10% delay overhead and to 1.0 V for only about 20% delay overhead.

117 citations


Journal ArticleDOI
TL;DR: This paper considers early prediction of net activity and interconnect capacitance in field-programmable gate array (FPGA) designs and develops empirical prediction models for these parameters, suitable for use in power-aware layout synthesis, early power estimation/planning, and other applications.
Abstract: The dynamic power consumed by a digital CMOS circuit is directly proportional to both switching activity and interconnect capacitance. In this paper, we consider early prediction of net activity and interconnect capacitance in field-programmable gate array (FPGA) designs. We develop empirical prediction models for these parameters, suitable for use in power-aware layout synthesis, early power estimation/planning, and other applications. We examine how switching activity on a net changes when delays are zero (zero delay activity) versus when logic delays are considered (logic delay activity) versus when both logic and routing delays are considered (routed delay activity). We then describe a novel approach for prelayout activity prediction that estimates a net's routed delay activity using only zero or logic delay activity values, along with structural and functional circuit properties. For capacitance prediction, we show that prediction accuracy is improved by considering aspects of the FPGA interconnect architecture in addition to generic parameters, such as net fanout and bounding box perimeter length. We also demonstrate that there is an inherent variability (noise) in the switching activity and capacitance of nets that limits the accuracy attainable in prediction. Experimental results show the proposed prediction models work well given the noise limitations.

104 citations


Journal ArticleDOI
Leendert M. Huisman1
TL;DR: A new form of logic diagnosis is described that is suitable for diagnosing fails in combinational logic and can diagnose failures caused by bridges and opens as well as fails caused by regular stuck-at faults.
Abstract: A new form of logic diagnosis is described that is suitable for diagnosing fails in combinational logic. It can diagnose defects that can affect arbitrarily many elements in the integrated circuit. It operates by first identifying patterns during which only one element is affected by the defect, and then diagnosing the fails observed during the application of such patterns, one pattern at a time. Single stuck-at faults are used for this purpose, and the aggregate of stuck-at fault locations thus identified is then further analyzed to obtain the most accurate estimate of the identities of those elements that can be affected by the defect. This approach to logic diagnosis is as effective as that of classical stuck-at fault-based diagnosis, when the latter applies, but is far more general. In particular, it can diagnose fails caused by bridges and opens as well as fails caused by regular stuck-at faults.

99 citations


Proceedings ArticleDOI
07 Nov 2004
TL;DR: The technique, which decouples the physical from the logical aspects of soft error susceptibility of a gate, uses a gate (transistor) sizing technique that is both efficient and accurate (in comparison to SPICE).
Abstract: A radiation hardening technique for combinational logic circuits is described. The key idea is to exploit the asymmetric logical masking probabilities of gates, hardening gates that have the lowest logical masking probability to achieve cost-effective tradeoffs between overhead and soft error failure rate reduction. The technique, which decouples the physical from the logical aspects of soft error susceptibility of a gate, uses a gate (transistor) sizing technique that is both efficient and accurate (in comparison to SPICE). A full set of experimental results demonstrate the cost-effective tradeoffs that can be achieved.

90 citations


Journal ArticleDOI
20 Sep 2004
TL;DR: Recent advances of SFQ circuit design technologies and recent developments of switches for high-end routers and microprocessors forhigh-end computers that are considered possible applications for SFQ logic will be described.
Abstract: Single-flux quantum logic (SFQ) circuits, in which a flux quantum is used as an information carrier, have the possibility for opening the door to a new digital system operated at over 100-GHz clock frequency at extremely low power dissipation. The SFQ logic system is a so-called pulse logic, which is completely different from the level logic for semiconductors like CMOS, so circuit design technologies for SFQ logic circuits have to be newly developed. Recently, much progress in basic technologies for designing SFQ circuits and operating circuits at high speeds has been made. With advances in these design tools, large-scale circuits including more than several thousand junctions can be easily operated with the clock frequency of more than several tens of gigahertz. High-end routers and high-end computers are possible applications of SFQ logic circuits because of their high throughput nature and the low power dissipation of SFQ logic. In this paper, recent advances of SFQ circuit design technologies and recent developments of switches for high-end routers and microprocessors for high-end computers that are considered possible applications for SFQ logic will be described.

82 citations


Journal ArticleDOI
18 Jul 2004
TL;DR: In this paper, it is argued that moving from evolutionary design for experimentation to design-for-implementation requires, beyond inclusion in the fitness function of measures indicative of circuit evaluation factors such as power consumption and robustness to temperature variations, the addition of certain evaluation techniques that are not common in conventional design.
Abstract: Current techniques in evolutionary synthesis of analogue and digital circuits designed at transistor level have focused on achieving the desired functional response, without paying sufficient attention to issues needed for a practical implementation of the resulting solution. No silicon fabrication of circuits with topologies designed by evolution has been done before, leaving open questions on the feasibility of the evolutionary circuit design approach, as well as on how high-performance, robust, or portable such designs could be when implemented in hardware. It is argued that moving from evolutionary 'design-for experimentation' to 'design-for-implementation' requires, beyond inclusion in the fitness function of measures indicative of circuit evaluation factors such as power consumption and robustness to temperature variations, the addition of certain evaluation techniques that are not common in conventional design. Several such techniques that were found to be useful in evolving designs for implementation are presented; some are general, and some are particular to the problem domain of transistor-level logic design, used here as a target application. The example used here is a multifunction NAND/NOR logic gate circuit, for which evolution obtained a creative circuit topology more compact than what has been achieved by multiplexing a NAND and a NOR gate. The circuit was fabricated in a 0.5 mum CMOS technology and silicon tests showed good correspondence with the simulations.

81 citations


Journal ArticleDOI
28 Jun 2004
TL;DR: A mixed-signal programmable chip for high-speed vision applications that can capture an image, run approximately 150 two-dimensional linear convolutions, and download the result in 8-bit digital format in less than 1 ms, together with the possibility of executing sequences of user-definable instructions makes the chip a true general-purpose sensory/processing device.
Abstract: This paper presents a mixed-signal programmable chip for high-speed vision applications. It consists of an array of processing elements, arranged to operate in accordance with the principles of single instruction multiple data (SIMD) computing architectures. This chip, implemented in a 0.35-/spl mu/m fully digital CMOS technology, contains /spl sim/ 3.75 M transistors and exhibits peak performance figures of 330 GOPS (8-bit equivalent giga-operations per second), 3.6 GOPS/mm/sup 2/ and 82.5 GOPS/W. It includes structures for image acquisition and for image processing, meaning that it does not require a separate imager for operation. At the sensory side, integration and log-compression sensing circuits are embedded, thus allowing the chip to handle a large variety of illumination conditions. At the processing plane, analog and digital circuits are employed whose parameters can be programmed and their architecture reconfigured for the realization of software-coded processing algorithms. The chip provides, and accepts, 8-bit digitized data through a 32-bit bidirectional data bus which operates at 120 MB/s. Experimental results show that frame rates of 1000 frames per second (FPS) can be achieved under room illumination conditions; applications using exposures of about 50 /spl mu/s have been recently reached by using special illumination setups. The chip can capture an image, run approximately 150 two-dimensional linear convolutions, and download the result in 8-bit digital format, in less than 1 ms. This feature, together with the possibility of executing sequences of user-definable instructions (stored on a full-custom 32-kb on-chip memory), and storing intermediate results (up to 8 grayscale images) makes the chip a true general-purpose sensory/processing device.

79 citations


Journal ArticleDOI
20 Sep 2004
TL;DR: The process technologies and fabrication methodologies for digital superconductor integrated circuits are described and the key developments required for the next generation of 100-GHz logic circuits are discussed.
Abstract: Today's superconductor integrated circuit processes are capable of fabricating large digital logic chips with more than 10 K gates/cm/sup 2/. Recent advances in process technology have come from a variety of industrial foundries and university research efforts. These advances in processing have reduced critical current spreads and increased circuit speed, density, and yield. On-chip clock speeds of 60 GHz for complex digital logic and 750 GHz for a static divider (toggle flip-flop) have been demonstrated. Large digital logic circuits, with Josephson junction counts greater than 60 k, have also been fabricated using advanced foundry processes. Circuit yield is limited by defect density, not by parameter spreads. The present level of integration is limited largely by wiring and interconnect density and not by junction density. The addition of more wiring layers is key to the future development of this technology. We describe the process technologies and fabrication methodologies for digital superconductor integrated circuits and discuss the key developments required for the next generation of 100-GHz logic circuits.

Patent
26 Feb 2004
TL;DR: In this paper, a combinational logic path includes two types of logic blocks cells that compensate each other for fabrication parameter effects on cell transistors, and the two types may be dense cells with field effect transistor (FET) gates on contacted pitch and isolated cells with FET gates on wider than contacted pitch.
Abstract: An integrated circuit (IC) including at least one combinational logic path. The combinational logic path includes two types of logic blocks cells that compensate each other for fabrication parameter effects on cell transistors. The two types may be dense cells with field effect transistor (FET) gates on contacted pitch and isolated cells with FET gates on wider than contacted pitch. Dense cell delay changes from the FET gates being printed out of focus are offset by isolated cell delay changes.

Patent
17 May 2004
TL;DR: In this paper, a method of forming a semiconductor device includes fabricating digital circuits comprising a programmable logic circuit on a substrate, selectively fabricating either a memory circuit or a conductive pattern substantially above the digital circuits to program the programmable circuit, and fabricating a common interconnect and routing layer substantially above both digital circuits and memory circuits.
Abstract: A method of forming a semiconductor device includes fabricating digital circuits comprising a programmable logic circuit on a substrate; selectively fabricating either a memory circuit or a conductive pattern substantially above the digital circuits to program said programmable logic circuit; and fabricating a common interconnect and routing layer substantially above the digital circuits and memory circuits to connect digital circuits and one of the memory circuit or the conductive pattern.

Journal ArticleDOI
TL;DR: This paper investigates single electron encoded logic (SEEL) memory circuits, in which the Boolean logic values are encoded as zero or one electron charges, and presents a generic SEEL linear threshold gate implementation, from which a family of Boolean logic gates are derived.
Abstract: Single electron tunneling (SET) technology offers the ability to control the transport of individual electrons. In this paper, we investigate single electron encoded logic (SEEL) memory circuits, in which the Boolean logic values are encoded as zero or one electron charges. More specifically, we focus on the implementation of SEEL latches and flip-flops. All proposed circuits are verified by means of simulation using the SIMulation Of Nanostructures package. We first present a generic SEEL linear threshold gate implementation, from which we derive a family of Boolean logic gates. Second, we propose Boolean gate-based implementations of the RS latch, the D latch, and D flip-flop. Third, we propose threshold gate-based implementations of the same memory elements. Finally, we discuss the estimated area, delay, and power consumption of the Boolean gate-based and threshold gate-based implementations, and compare them with other SET-based memory elements.

Proceedings ArticleDOI
11 Oct 2004
TL;DR: A technique for creating a combinational logic network with an output that signals when all other outputs have stabilized, based on dual-rail encoding, and guarantees low timing overhead and reasonable area and power overhead is proposed.
Abstract: This paper proposes a technique for creating a combinational logic network with an output that signals when all other outputs have stabilized. The method is based on dual-rail encoding, and guarantees low timing overhead and reasonable area and power overhead. We discuss various scenarios in which completion detection can be used to measure the delay of a synchronous circuit at fabrication time or at run time, and of an asynchronous circuit at run time. We conclude by showing, on a large set of benchmarks, the effectiveness of the proposed technique.

Book ChapterDOI
01 Dec 2004
TL;DR: A VLSI convolutional network architecture using a hybrid approach composed of pulse-width modulation (PWM) and digital circuits is proposed, which is called merged/mixed analog-digital architecture.
Abstract: Hierarchical convolutional neural networks represent a well-known robust image-recognition model. In order to apply this model to robot vision or various intelligent vision systems, its VLSI implementation with high performance and low power consumption is required. This paper proposes a VLSI convolutional network architecture using a hybrid approach composed of pulse-width modulation (PWM) and digital circuits. We call this approach merged/mixed analog-digital architecture. The VLSI chip includes PWM neuron circuits, PWM/digital converters, digital adder-subtracters, and digital memory. We have designed and fabricated a VLSI chip by using a 0.35 μm CMOS process. The VLSI chip can perform 6-bit precision convolution calculations for an image of 100 × 100 pixels with a receptive field area of up to 20 × 20 pixels within 5 ms, which means a performance of 2 GOPS. Power consumption of PWM neuron circuits was measured to be 20 mW. We have verified successful operations using a fabricated VLSI chip.

Journal ArticleDOI
TL;DR: This paper will summarize how the same design process methodology that has been applied in developing complementary metal-oxide semiconductor circuits over the past twenty years was used in the development of quantum-dot cellular automata circuits, resulting in a more efficient design process.
Abstract: As the size and complexity of quantum-dot cellular automata (QCA) digital circuits increase, the amount of time needed to create a QCA layout and then simulate the quasi-adiabatic switching of that layout significantly increases. To help reduce this development time, the same design process methodology that has been applied in developing complementary metal-oxide semiconductor circuits over the past twenty years can be used in the development of QCA circuits. This methodology involves creating and verifying the circuits at higher levels of abstraction before they are implemented and verified at the device level. By following this methodology, QCA circuits can be developed and verified at a behavioral and structural level before they are implemented at a cellular level. Functional errors at these higher levels can quickly be detected and corrected so that when the quasi-adiabatic simulations are performed the circuits will perform properly. By finding these errors early in the process, the overall time to create and verify complex devices should be decreased. In this paper, we will summarize how this methodology was used in the design, layout, and simulation of a medium-scale QCA device that accepts a serial stream of data and monitors the data for a particular serial pattern of bits. Very-high-speed integrated circuit (VHSIC) hardware description language (VHDL) models were developed to represent and verify the QCA circuits before the cellular-level simulation was performed. First, behavioral VHDL models were used to verify the input/output operation of the different blocks in the circuit. Then, a VHDL library was created containing design entities that implement the different QCA interactions. This library was used to develop and verify a structural VHDL model that represented the initial QCA layout. Finally, after all the VHDL models were verified, the QCA circuit was then simulated using a more thorough simulation based on quantum mechanics. Using this methodology resulted in a more efficient design process, as design errors were detected much earlier in the development cycle.

Journal ArticleDOI
TL;DR: A concept of random masking of arbitrary logic circuits on the logic gate level is developed and several techniques are proposed, important for protecting hardware implementations of cryptographic algorithms against side-channel attacks.
Abstract: A concept of random masking of arbitrary logic circuits on the logic gate level is developed and several techniques are proposed. The results are important for protecting hardware implementations of cryptographic algorithms against side-channel attacks.

Journal ArticleDOI
TL;DR: An approach based on an evolutionary algorithm to design synchronous sequential logic circuits with minimum number of logic gates is suggested and the obtained results compare favourably against those produced by manual methods and other methods based on heuristic techniques.
Abstract: In this paper an approach based on an evolutionary algorithm to design synchronous sequential logic circuits with minimum number of logic gates is suggested. The proposed method consists of four main stages. The first stage is concerned with the use of genetic algorithms (GA) for the state assignment problem to compute optimal binary codes for each symbolic state and construct the state transition table of finite state machine (FSM). The second stage defines the subcircuits required to achieve the desired functionality. The third stage evaluates the subcircuits using extrinsic Evolvable Hardware (EHW). During the fourth stage, the final circuit is assembled. The obtained results compare favourably against those produced by manual methods and other methods based on heuristic techniques.

Book
15 Jul 2004
TL;DR: Fundamentals of Digital Logic With VHDL Design teaches the basic design techniques for logic circuits, and emphasizes the synthesis of circuits and explains how circuits are implemented in real chips.
Abstract: Fundamentals of Digital Logic With VHDL Design teaches the basic design techniques for logic circuits. It emphasizes the synthesis of circuits and explains how circuits are implemented in real chips. Fundamental concepts are illustrated by using small examples, which are easy to understand. Then, a modular approach is used to show how larger circuits are designed. VHDL is used to demonstrate how the basic building blocks and larger systems are defined in a hardware description language, producing designs that can be implemented with modern CAD tools. The book emphasizes the concepts that should be covered in an introductory course on logic design, focusing on: Logic functions, gates, and rules of Boolean algebra Circuit synthesis and optimization techniques Number representation and arithmetic circuits Combinational-circuit building blocks, such as multiplexers, decoders, encoders, and code converters Sequential-circuit building blocks, such as flip-flops, registers, and counters Design of synchronous sequential circuits Use of the basic building blocks in designing larger systems It also includes chapters that deal with important, but more advanced topics: Design of asynchronous sequential circuits Testing of logic circuits For students who have had no exposure to basic electronics, but are interested in learning a few key concepts, there is a chapter that presents the most basic aspects of electronic implementation of digital circuits. Major changes in the second edition of the book include new examples to clarify the presentation of fundamental concepts over 50 new examples of solved problems provided at the end of chapters NAND and NOR gates now introduced in Chapter 2 more complete discussion of techniques for minimization of logic functions in Chapter 4 (including the tabular method) a new chapter explaining the CAD flow for synthesis of logic circuits Altera's Quartus II CAD software provided on a CD-ROM three appendices that give tutorials on the use of Quartus II software Table of contents 1 Design Concepts 2 Introduction to Logic Circuits 3 Implementation Technology 4 Optimized Implementation of Logic Functions 5 Number Representation and Arithmetic Circuits 6 Combinational-Circuit Building Blocks 7 Flip-Flops, Registers, Counters, and a Simple Processor 8 Synchronous Sequential Circuits 9 Asynchronous Sequential Circuits 10 Digital System Design 11 Testing of Logic Circuits 12 Computer Aided Design Tools Appendix A VHDL Reference Appendix B Tutorial 1 - Using Quartus II CAD Software Appendix C Tutorial 2 - Implementing Circuits in Altera Devices Appendix D Tutorial 3 - Physical Implementations in a PLD Appendix D Commercial Devices

Proceedings ArticleDOI
10 Oct 2004
TL;DR: Three new reversible logic gates can be used to implement reversible digital circuits of various levels of complexity and provide on-line testability for circuits implemented using them.
Abstract: A technique for an on-line testable reversible logic circuit is presented. Three new reversible logic gates have been introduced in this paper. These gates can be used to implement reversible digital circuits of various levels of complexity. The major feature of these gates is that they provide on-line testability for circuits implemented using them. The application of these gates in implementation of a subset of MCNC benchmark circuits is provided.

Patent
Jovan Golic1
09 Aug 2004
TL;DR: In this article, a random binary sequence generator for generating random numbers is defined, where at least one logic circuit corresponds to an associated finite-state machine having a statetransition function including states arranged to form cycles of states.
Abstract: A random binary sequence generator (105) for generating a random binary sequence (RRBS) adapted to be used for producing random numbers, comprising at least one logic circuit (115) corresponding to an associated finite-state machine having a statetransition function including states arranged to form cycles of states, wherein: the at least one logic circuit has a set of logic circuit inputs (In) and a set of logic circuit outputs (Out) fed back to said logic circuit inputs; the associated finite-state machine is autonomous and asynchronous; the state-transition function is void of loops; and any of the cycles of states has either a minimum length equal to three states, in case the cycle is stable, or a minimum length of two states, in case the cycle is meta-stable.

Journal ArticleDOI
C. Hacker1, R. Sitte1
TL;DR: This suite fills a perceived gap in the currently available computer-based teaching software, with the purpose of providing alternative-mode subject delivery, comprising a set of interactive tutorials that show the link between Boolean algebra and digital combinatorial and sequential circuits.
Abstract: This paper presents an interactive computerized teaching suite developed for the design of combinatorial and sequential logic circuits. This suite fills a perceived gap in the currently available computer-based teaching software, with the purpose of providing alternative-mode subject delivery. The authors were, therefore, prompted to develop a Microsoft-Windows tutorial suite, WinLogiLab, comprising a set of interactive tutorials that show the link between Boolean algebra and digital combinatorial and sequential circuits. The combinatorial tutorials follow the initial design steps: from Boolean algebra, to truth tables, to minimization techniques, to production of the combinatorial circuit in a seamless way. Similarly, the sequential tutorials can design simple finite-state counters and can model more complex finite-state automata.

Journal ArticleDOI
TL;DR: In this paper, a digital circuit using polymer thin-film transistors on polyester substrate is presented, which consists of 171 transistors and converts a parallel word of four bits into a serial bit sequence by use of gates and flip-flops with level shifters.
Abstract: A digital circuit using polymer thin-film transistors on polyester substrate is presented. The circuit consists of 171 transistors and converts a parallel word of four bits into a serial bit sequence by use of gates and flip-flops with level shifters. The integrated clock generator runs at oscillation frequencies of approximately 200 Hz with supply voltages of -25 V/+12 V. The polymer poly(3,3''-dihexyl-2,2':5',2''-terthiophene) (PDHTT) is used as semiconducting material. Measurement results for the circuit demonstrate that PDHTT can be used for digital polymer circuits.

Journal ArticleDOI
18 Jul 2004
TL;DR: The evolved multiplier and adder circuits show a graceful degradation as noise and failrate are increased and the robustness and tolerance of bio-inspired hardware systems are illustrated.
Abstract: Artificial evolution has been shown to generate remarkable systems of exciting novelty. It is able to automatically generate digital circuit designs and even circuits that are robust to noise and faults. Extensive experiments have been carried out and are presented here to identify more clearly to what extent artificial evolution is able to generate robust designs. The evolved circuits are thoroughly tested whilst being exposed to noise and faults in a simulated environment and the results of their performance are presented. The evolved multiplier and adder circuits show a graceful degradation as noise and failrate are increased. The functionality of all circuits is measured in a simulated environment that to some extent takes into account analogue electronic properties. Also included is a short overview of some recent work illustrating the robustness and tolerance of bio-inspired hardware systems.

Proceedings ArticleDOI
27 Sep 2004
TL;DR: This paper reviews active and passive elements of CMOS MS/RF SoC technology from a scaling perspective and finds improvements in passive-component performance metrics consistent with fundamental scaling trends.
Abstract: The development of short-range wireless communication has become exceedingly important due to the emerging market of WLAN and Bluetooth. CMOS technology has emerged as the top solution due to its cost advantage, performance improvement and ease of integration for high-performance digital circuits and high-speed analog/RF circuits. Accelerated scaling of CMOS technology has contributed to remove otherwise fundamental barriers preempting its widespread application to mixed-signal/radio-frequency (MS/RF) segments. Improvements in device speed, matching, and minimum noise figure are all consistent with fundamental scaling trends. Other figures-of-merit such as linearity and 1/f noise do not scale favorably but are not considered roadblocks when viewed from a circuit design perspective. Furthermore, interconnect architectural scaling trends in logic technology have facilitated improvements in passive-component performance metrics. These improvements compounded with innovations in circuit design have made CMOS technology the primary choice for cost driven MS/RF applications. This paper reviews active and passive elements of CMOS MS/RF SoC technology from a scaling perspective.

Journal ArticleDOI
TL;DR: In this article, the dependence of the Vdd-Vss admittance on the different states of the circuit, the supply voltage, and the interconnect was investigated and the computation of the total supply current with ground bounce was performed.
Abstract: Substrate noise is a major obstacle for mixed-signal integration. Ground bounce is a major contributor to substrate noise generation due to the resonance caused by the inductance and the Vdd-Vss admittance that consists of the on-chip digital circuit capacitance of the MOS transistors, the decoupling, and the parasitics arising from the interconnect. In this paper, we address: 1) the dependence of the Vdd-Vss admittance on the different states of the circuit, the supply voltage, and the interconnect, and 2) the computation of the total supply current with ground bounce. By using a fast and accurate macromodeling approach, the Vdd-Vss admittances of several test circuits are computed with 2%-3% error relative to the values simulated from the complete SPICE level netlist, but several orders of magnitude faster in CPU time and with 10% maximum error relative to the measurements on a test ASIC fabricated in a 0.18-/spl mu/m CMOS process on a high-ohmic substrate with 18 /spl Omega//spl middot/cm resistivity. The measurements also show that this admittance mainly depends only on the connectivity of the gates to the supply rail rather than their connectivity among each other.

Proceedings ArticleDOI
31 Aug 2004
TL;DR: This paper describes an efficient approach to the automatic design of networks of threshold gates from functional specifications and results for widely used logic functions and standard benchmark circuits are reported.
Abstract: Functional devices and circuits based on resonant tunneling diodes (RTD) are receiving much attention since they allow high speed and/or low power operation. RTDs exhibit a negative differential resistance in their current-voltage characteristic which can be exploited to significantly increase the functionality implemented by a single gate in comparison to other technologies. In particular, they have proven to efficiently implement threshold gates which are a generalization of conventional Boolean gates. Suitable logic synthesis tools are required to handle these complex building blocks in order to translate the advantages of this emergent technology to the circuit and system levels. This paper describes an efficient approach to the automatic design of networks of threshold gates from functional specifications. Results for widely used logic functions and standard benchmark circuits are reported.

Journal ArticleDOI
Dongmyung Lee1, Kwisung Yoo1, Kicheol Kim1, Gunhee Han1, Sungho Kang1 
TL;DR: A new analog-to-digital converter built-in self-test (BIST) scheme based on code-width and sample-difference testing that does not require a slope-calibrated ramp signal is proposed.
Abstract: This paper proposes a new analog-to-digital converter (ADC) built-in self-test (BIST) scheme based on code-width and sample-difference testing that does not require a slope-calibrated ramp signal. The proposed BIST scheme can be implemented by a simple digital circuit whose gate count is only approximately 550. The proposed BIST scheme is verified by simulation with 138 test circuits of 6-b pipeline ADC with arbitrary faults. Simulation results show that it effectively detects not only the catastrophic faults but also some parametric faults. The simulated fault coverage is approximately 99%.

Proceedings ArticleDOI
17 May 2004
TL;DR: Implementation results are provided to demonstrate that a high-speed, low logic complexity LMS adaptive filter can be realized employing the proposed architecture.
Abstract: In this paper, an FIR adaptive filter implementation, using a multiplier-free architecture, is presented. The implementation is based on distributed arithmetic (DA) which substitutes multiply-and-accumulate operations with a series of look-up-table (LUT) accesses. This can be achieved at the cost of a moderate increase in memory usage. The proposed design performs an LMS-type adaptation on a sample-by-sample basis. This is accomplished by an innovative LUT update using a matched auxiliary LUT. The system is implemented on an FPGA that enables rapid prototyping of digital circuits. Implementation results are provided to demonstrate that a high-speed, low logic complexity LMS adaptive filter can be realized employing the proposed architecture.