Showing papers on "Digital electronics published in 2008"

High-Level Synthesis: from Algorithm to Digital Circuit

Abstract: This book presents an excellent collection of contributions addressing different aspects of high-level synthesis from both industry and academia. High-Level Synthesis: from Algorithm to Digital Circuit should be on each designers and CAD developers shelf, as well as on those of project managers who will soon embrace high level design and synthesis for all aspects of digital system design.

Nanometer MOSFET Variation in Minimum Energy Subthreshold Circuits

Abstract: Minimum energy operation for digital circuits typically requires scaling the power supply below the device threshold voltage. Advanced technologies offer improved integration, performance, and active-energy efficiency for minimum energy sub-Vt circuits, but are plagued by increased variation and reduced ION/IOFF ratios, which degrade the fundamental device characteristics critical to circuit operation by several orders of magnitude. This paper investigates those characteristics and presents design methodologies and circuit topologies to manage their severe degradation. The issues specific to both general logic and dense static random access memories are analyzed, and solutions that address their distinct design metrics are presented.

Digital Circuit Design Challenges and Opportunities in the Era of Nanoscale CMOS : Small transistors necessitate big changes, in the way digital circuits are modeled and optimized for manufacturability, and new strategies for logic, memory, clocking and power distribution

Abstract: Well-designed circuits are one key Binsulating( layer between the increasingly unruly behavior of scaled complementary metal-oxide-semiconductor devices and the systems we seek to construct from them. As we move forward into the nanoscale regime, circuit design is burdened to Bhide( more of the problems intrinsic to deeply scaled devices. How this is being accomplished is the subject of this paper. We discuss new techniques for logic circuits and interconnect, for memory, and for clock and power distribution. We survey work to build accurate simulation models for nanoscale devices. We discuss the unique problems posed by nanoscale lithography and the role of geometrically regular circuits as one promising solution. Finally, we look at recent computer-aided design efforts in modeling, analysis, and optimization for nanoscale designs with ever increasing amounts of statistical variation.

Digital Circuit Design Challenges and Opportunities in the Era of Nanoscale CMOS

Abstract: Well-designed circuits are one key ldquoinsulatingrdquo layer between the increasingly unruly behavior of scaled complementary metal-oxide-semiconductor devices and the systems we seek to construct from them. As we move forward into the nanoscale regime, circuit design is burdened to ldquohiderdquo more of the problems intrinsic to deeply scaled devices. How this is being accomplished is the subject of this paper. We discuss new techniques for logic circuits and interconnect, for memory, and for clock and power distribution. We survey work to build accurate simulation models for nanoscale devices. We discuss the unique problems posed by nanoscale lithography and the role of geometrically regular circuits as one promising solution. Finally, we look at recent computer-aided design efforts in modeling, analysis, and optimization for nanoscale designs with ever increasing amounts of statistical variation.

Digital Integrated Circuit Design: From VLSI Architectures to CMOS Fabrication

Abstract: VLSI circuits are ubiquitous in the modern world, and designing them efficiently is becoming increasingly challenging with the development of ever smaller chips. This practically oriented textbook covers the important aspects of VLSI design using a top-down approach, reflecting the way digital circuits are actually designed. Using practical hints and tips, case studies and checklists, this comprehensive guide to how and when to design VLSI circuits, covers the advances, challenges and past mistakes in design, acting as an introduction to graduate students and a reference for practising electronic engineers.

Modeling and Simulation of Single-Event Effects in Digital Devices and ICs

Abstract: This paper reviews the status of research in modeling and simulation of single-event effects (SEE) in digital devices and integrated circuits, with a special emphasis on the current challenges concerning the physical modeling of ultra-scaled devices (in the deca-nanometer range) and new device architectures (Silicon-on-insulator, multiple-gate, nanowire MOSFETs). After introducing the classification and the terminology used in this paper, we firstly present the basis of the different transport models used in device-level simulation (drift-diffusion, hydrodynamic, Monte-Carlo and some approximated and exact quantum-mechanical based approaches). We also focus on the main emerging physical phenomena affecting ultra-short MOSFETs (quantum effects, tunneling current, ballistic operation) and the methods envisaged for taking them into account at device simulation level. Several examples of device simulation are given at the end of this first part, including recent results on fully-depleted SOI and multiple-gate devices. In the second part, we briefly survey the different circuit-level modeling approaches (circuit-level simulation, Mixed-Mode, 3-D simulation of portions of circuits) of single-event effects in integrated circuits. The SEU in advanced SRAM and SEE mechanisms in logic circuits are reminded. The production and propagation of digital single-event transients (DSETs) in sequential and combinational logic, as well as the soft error rate trends with scaling are particularly addressed. Recent bibliographical examples of simulation in SRAMs and logic circuits are presented and discussed to illustrate these topics at circuit-level.

All-optical half adder based on cross structures in two-dimensional photonic crystals.

Abstract: We propose an all-optical half adder based on two different cross structures in two-dimensional photonic crystals. One cross structure contains nonlinear materials and functions as an "AND" logic gate. The other one only contains linear materials and acts as an "XOR" logic gate. The system is demonstrated numerically by the FDTD method to work as expected. The optimal operating speed without considering the response time of the nonlinear material, the least ON to OFF logic-level contrast ratio, and the minimum power for this half adder obtained were 0.91 Tbps, 16 dB and 436 mW, respectively. The proposed structure has the potential to be used for constructing all-optical integrated digital computing circuits.

Next generation micro-power systems

Abstract: Emerging microsystems such as portable and implantable medical electronics, wireless microsensors and next-generation portable multimedia devices demand a dramatic reduction in energy consumption. The ultimate goal is to power these devices using energy harvesting techniques such as vibration-to-electric conversion or through wireless power transmission. A major opportunity to reduce the energy consumption of digital circuits is to scale supply voltages to 0.5V and below. The challenges associated with ultra-low-voltage design will be presented. These include variation-aware design for logic and SRAM circuits, efficient DC-DC converters for ultra-low-voltage delivery, and algorithm structuring to support extreme parallelism. This paper also addresses micro-power analog and RF circuits, which require the use of application-specific structures and highly digital variation-aware architectures.

The synthesis of robust polynomial arithmetic with stochastic logic

Abstract: As integrated circuit technology plumbs ever greater depths in the scaling of feature sizes, maintaining the paradigm of deterministic Boolean computation is increasingly challenging. Indeed, mounting concerns over noise and uncertainty in signal values motivate a new approach: the design of stochastic logic, that is to say, digital circuitry that processes signals probabilistically, and so can cope with errors and uncertainty. In this paper, we present a general methodology for synthesizing stochastic logic for the computation of polynomial arithmetic functions, a category that is important for applications such as digital signal processing. The method is based on converting polynomials into a particular mathematical form --- Bernstein polynomials --- and then implementing the computation with stochastic logic. The resulting logic processes serial or parallel streams that are random at the bit level. In the aggregate, the computation becomes accurate, since the results depend only on the precision of the statistics. Experiments show that our method produces circuits that are highly tolerant of errors in the input stream, while the area-delay product of the circuit is comparable to that of deterministic implementations.

Superconductor Digital-RF Receiver Systems

Abstract: Digital superconductor electronics has been experiencing rapid maturation with the emergence of smaller-scale, lower-cost communications applications which became the major technology drivers These applications are primarily in the area of wireless communications, radar, and surveillance as well as in imaging and sensor systems In these areas, the fundamental advantages of superconductivity translate into system benefits through novel Digital-RF architectures with direct digitization of wide band, high frequency radio frequency (RF) signals At the same time the availability of relatively small 4K cryocoolers has lowered the foremost market barrier for cryogenically-cooled digital electronic systems Recently, we have achieved a major breakthrough in the development, demonstration, and successful delivery of the cryocooled superconductor digital-RF receivers directly digitizing signals in a broad range from kilohertz to gigahertz These essentially hybrid-technology systems combine a variety of superconductor and semiconductor technologies packaged with two-stage commercial cryocoolers: cryogenic Nb mixed-signal and digital circuits based on Rapid Single Flux Quantum (RSFQ) technology, room-temperature amplifiers, FPGA processing and control circuitry The demonstrated cryocooled digital-RF systems are the world's first and fastest directly digitizing receivers operating with live satellite signals in X-band and performing signal acquisition in HF to L-band at ∼30GHz clock frequencies

On Real-Time AER 2-D Convolutions Hardware for Neuromorphic Spike-Based Cortical Processing

Abstract: In this paper, a chip that performs real-time image convolutions with programmable kernels of arbitrary shape is presented. The chip is a first experimental prototype of reduced size to validate the implemented circuits and system level techniques. The convolution processing is based on the address-event-representation (AER) technique, which is a spike-based biologically inspired image and video representation technique that favors communication bandwidth for pixels with more information. As a first test prototype, a pixel array of 16times16 has been implemented with programmable kernel size of up to 16times16. The chip has been fabricated in a standard 0.35 mum complimentary metal-oxide-semiconductor (CMOS) process. The technique also allows to process larger size images by assembling 2D arrays of such chips. Pixel operation exploits low-power mixed analog-digital circuit techniques. Because of the low currents involved (down to nanoamperes or even picoamperes), an important amount of pixel area is devoted to mismatch calibration. The rest of the chip uses digital circuit techniques, both synchronous and asynchronous. The fabricated chip has been thoroughly tested, both at the pixel level and at the system level. Specific computer interfaces have been developed for generating AER streams from conventional computers and feeding them as inputs to the convolution chip, and for grabbing AER streams coming out of the convolution chip and storing and analyzing them on computers. Extensive experimental results are provided. At the end of this paper, we provide discussions and results on scaling up the approach for larger pixel arrays and multilayer cortical AER systems.

Compact hardware liquid state machines on FPGA for real-time speech recognition

Abstract: Hardware implementations of Spiking Neural Networks are numerous because they are well suited for implementation in digital and analog hardware, and outperform classic neural networks. This work presents an application driven digital hardware exploration where we implement real-time, isolated digit speech recognition using a Liquid State Machine. The Liquid State Machine is a recurrent neural network of spiking neurons where only the output layer is trained. First we test two existing hardware architectures which we improve and extend, but that appears to be too fast and thus area consuming for this application. Next, we present a scalable, serialized architecture that allows a very compact implementation of spiking neural networks that is still fast enough for real-time processing. All architectures support leaky integrate-and-fire membranes with exponential synaptic models. This work shows that there is actually a large hardware design space of Spiking Neural Network hardware that can be explored. Existing architectures have only spanned part of it.

Energy Consumption Estimation in Embedded Systems

Abstract: This paper presents an energy consumption modeling technique for embedded systems based on a microcontroller. The software tasks that run on the embedded system are profiled, and their characteristics are analyzed. The type of executed assembly instructions, as well as the number of accesses to the memory and the analog-to-digital converter, is the required information for the derivation of the proposed model. An appropriate instrumentation setup has been developed for measuring and modeling the energy consumption in the corresponding digital circuits.

On Real-Time AER 2-D Convolutions Hardware for

Abstract: In this paper, a chip that performs real-time image convolutions with programmable kernels of arbitrary shape is pre- sented. The chip is a first experimental prototype of reduced size to validate the implemented circuits and system level techniques. The convolution processing is based on the address-event-rep- resentation (AER) technique, which is a spike-based biologically inspired image and video representation technique that favors communication bandwidth for pixels with more information. As a first test prototype, a pixel array of 16 16 has been imple- mented with programmable kernel size of up to 16 16. The chip has been fabricated in a standard 0.35- m complimentary metal-oxide-semiconductor (CMOS) process. The technique also allows to process larger size images by assembling 2-D arrays of such chips. Pixel operation exploits low-power mixed analog-dig- ital circuit techniques. Because of the low currents involved (down to nanoamperes or even picoamperes), an important amount of pixel area is devoted to mismatch calibration. The rest of the chip uses digital circuit techniques, both synchronous and asyn- chronous. The fabricated chip has been thoroughly tested, both at the pixel level and at the system level. Specific computer interfaces have been developed for generating AER streams from conven- tional computers and feeding them as inputs to the convolution chip, and for grabbing AER streams coming out of the convolution chip and storing and analyzing them on computers. Extensive experimental results are provided. At the end of this paper, we provide discussions and results on scaling up the approach for larger pixel arrays and multilayer cortical AER systems. Index Terms—Address-event representation (AER), analog circuits, asynchronous circuits, bioinspired systems, cortical layer processing, image convolutions, image processing, low power circuits, mixed-signal circuits, spike-based processing.

Digitally enhanced analog circuits: System aspects

Abstract: An overview of digital enhancement techniques for analog circuits is presented. Recent research suggests that the high density and low energy of digital circuits can be leveraged to enable a new generation of interface electronics that is based on minimal precision, low complexity analog blocks. Today, examples of enhancement schemes can be found in diverse applications and include nonlinearity compensation of ADCs, predistortion of power amplifiers and mismatch calibration in radio receivers. Since it is often difficult to identify commonalities among these different, but conceptually related schemes, this tutorial paper aims to provide a unified and system-oriented perspective of the field.

Digital Frequency Domain Multiplexer for Millimeter-Wavelength Telescopes

Abstract: An FPGA based digital signal processing (DSP) system for biasing and reading out multiplexed bolometric detectors for mm-wavelength telescopes is presented. This readout system is being deployed for balloon-borne and ground based cosmology experiments with the primary goal of measuring the signature of inflation with the Cosmic Microwave Background Radiation. The system consists of analog superconducting electronics running at 250 mK and 4 K, coupled to digital room temperature backend electronics described here. The digital electronics perform the real time functionality with DSP algorithms implemented in firmware. A soft embedded processor provides all of the slow housekeeping control and communications. Each board in the system synthesizes multi-frequency combs of 8 to 32 carriers in the MHz band to bias the detectors. After the carriers have been modulated with the sky-signal by the detectors, the same boards digitize the comb directly. The carriers are mixed down to base-band and low pass filtered. The signal bandwidth of 0.050 Hz-100 Hz places extreme requirements on stability and requires powerful filtering techniques to recover the sky-signal from the MHz carriers.

Integrated Regulation for Energy-Efficient Digital Circuits

Abstract: Despite their use in analog or mixed-signal applications, the high power overheads of traditional linear regulators (both series and shunt) have precluded their successful adoption in regulating the supply of energy-efficient digital circuits. In this paper, we show that linear regulation can in fact reduce the effective supply impedance of digital circuits without increasing their total power dissipation. Achieving this goal requires minimizing the static power dissipation of the regulator, leading to a push-pull topology (similar to the regulators demonstrated by Wu and Sanders, 2001, Poon et al, 1999, and Intersil, 1998) with comparator-based feedback and a switched source-follower output stage. Measured results from a regulator implemented in a 65 nm SOI test-chip verify that by using these techniques, regulation reduces the effective supply noise by ~30% while also enabling a slight decrease (1.4%) in total power dissipation.

LIFTING: A Flexible Open-Source Fault Simulator

Abstract: This paper presents LIFTING (LIRMM fault simulator), an open-source simulator able to perform both logic and fault simulations for single/multiple stuck-at faults and single event upset (SEU) on digital circuits described in Verilog. Compared to existing tools, LIFTING provides several features for the analysis of the fault simulation results, meaningful for research purposes. Moreover, as an open-source tool, it can be customized to meet any user requirements. Experimental results show how LIFTING has been exploited on research fields. Eventually, execution time for large circuit simulations is comparable to the one of commercial tools.

Practical Design Using Programmable Logic

Abstract: Part 1 Devices and tools: history a tour of PLDs beyond PLDs development tools. Part 2 Designing with PLDs: getting started applying digital logic high-level design techniques designing with FPGAs hazards, testability and metastability putting it all together.

A 6b 0.2-to-0.9V Highly Digital Flash ADC with Comparator Redundancy

Abstract: Microsensor wireless networks and implanted biomedical devices have emerged as exciting new application domains. These applications are highly energy constrained and require flexible, integrated, energy-efficient ADC modules that can ideally operate at the same supply voltage as digital circuits. In many applications, the performance requirements are quite modest (100s kS/s). This paper presents a highly digital ADC architecture compatible with advanced CMOS processes, capable of operating down to a supply voltage of 200mV (i.e., subthreshold regime) and up to 900mV. However, leakage and device variation must be addressed, particularly at low supply voltages.

On-Chip Measurement of Deep Metastability in Synchronizers

Abstract: A deep metastability measurement scheme has been implemented on chip using digital circuits with 0.18 mum technology. Compared with previous off-chip implementations using analog circuits, the on-chip implementation allows integration of both the synchronizer circuits and the measurement method, and eliminates high-speed off-chip paths which are a source of inaccuracy. It also makes control at the picosecond level easier because of the inherent stability of digital integrating counters and digital delay lines. Our results show that the digital delay line used to adjust the data to clock times is controllable to an increment of 0.1 ps, and the input time distribution is 5.2 ps compared with 7.6 ps for the analog version. Because of the use of high and low counters, we can control the ratio of high to low outputs so that the actual input distribution can be measured to within better than 1 ps. The metastability time constant tau has been measured down to 10-17 s which corresponds to an mean time between failures (MTBF) of 100 seconds in an experimental time of 10 minutes and can be extended to a lower level by increasing the measurement time. Our results also show that a new synchronizer circuit designed for robustness to variation in Vdd performed at least as well as the Jamb Latch at all values of Vdd, and is more than 20% faster when Vdd was reduced by 25%.

FSM-based Digital Design using Verilog HDL

Abstract: As digital circuit elements decrease in physical size, resulting in increasingly complex systems, a basic logic model that can be used in the control and design of a range of semiconductor devices is vital. Finite State Machines (FSM) have numerous advantages; they can be applied to many areas (including motor control, and signal and serial data identification to name a few) and they use less logic than their alternatives, leading to the development of faster digital hardware systems. This clear and logical book presents a range of novel techniques for the rapid and reliable design of digital systems using FSMs, detailing exactly how and where they can be implemented. With a practical approach, it covers synchronous and asynchronous FSMs in the design of both simple and complex systems, and Petri-Net design techniques for sequential/parallel control systems. Chapters on Hardware Description Language cover the widely-used and powerful Verilog HDL in sufficient detail to facilitate the description and verification of FSMs, and FSM based systems, at both the gate and behavioural levels. Throughout, the text incorporates many real-world examples that demonstrate designs such as data acquisition, a memory tester, and passive serial data monitoring and detection, among others. A useful accompanying CD offers working Verilog software tools for the capture and simulation of design solutions. With a linear programmed learning format, this book works as a concise guide for the practising digital designer. This book will also be of importance to senior students and postgraduates of electronic engineering, who require design skills for the embedded systems market.

WavePipe: parallel transient simulation of analog and digital circuits on multi-core shared-memory machines

Abstract: While the emergence of multi-core shared-memory machines offers a promising computing solution to ever complex chip design problems, new parallel CAD methodologies must be developed to gain the full benefit of these increasingly parallel computing systems. We present a parallel transient simulation methodology and its multi-threaded implementation for general analog and digital ICs. Our new approach, Waveform Pipelining (abbreviated as WavePipe), exploits coarsegrained application-level parallelism by simultaneously computing circuit solutions at multiple adjacent time points in a way resembling hardware pipelining. There are two embodiments in WavePipe: backward and forward pipelining schemes. While the former creates independent computing tasks that contribute to a larger future time step by moving backwards in time, the latter performs predictive computing along the forward direction of the time axis. Unlike existing relaxation methods, WavePipe facilitates parallel circuit simulation without jeopardying convergence and accuracy. As a coarse-grained parallel approach, WavePipe not only requires low parallel programming effort, more importantly, it creates new avenues to fully utilize increasingly parallel hardware by going beyond conventional finer grained parallel device model evaluation and matrix solutions.

Implementation of Basic Arithmetic Operations Using Cellular Automaton

Abstract: This paper presents hardware architecture to perform the basic arithmetic operation addition using cellular automata (CA). This age old problem of addition were previously solved by ripple circuit or carry look ahead circuit or by using a combination of them. Each of these circuits is purely combinational in nature and their complexity is centered on the number of logic gates and the associated gate delays. On the contrary, in our CA based design the complexity is mainly centered on the number of clock cycles required to finish the computation instead of the gate delays.

C-CREST Technique for Combinational Logic SET Testing

Abstract: SEUs due to combinational logic in 90 nm CMOS is analyzed at various speeds using a new design approach called the combinational circuit for radiation effects self-test (C-CREST). C-CREST allows the cross-section of combinational logic to be increased while minimizing propagation delay. The design was fabricated in IBM's 9SF CMOS process and underwent broadbeam testing that distinguished combinational logic errors from latch errors. Results confirm that the design is effective in testing combinational logic for SE vulnerabilities with minimum speed penalty.

Stochastic Digital Circuits for Probabilistic Inference

Abstract: We introduce combinational stochastic logic, an abstraction that generalizes deterministic digital circuit design (based on Boolean logic gates) to the probabilistic setting. We show how this logic can be combined with techniques from contemporary digital design to generate stateless and stateful circuits for exact and approximate sampling from a range of probability distributions. We focus on Markov chain Monte Carlo algorithms for Markov random fields, using massively parallel circuits. We implement these circuits on commodity reconfigurable logic and estimate the resulting performance in time, space and price. Using our approach, these simple and general algorithms could be affordably run for thousands of iterations on models with hundreds of thousands of variables in real time.

An Introduction to Logic Circuit Testing

Abstract: An Introduction to Logic Circuit Testing provides a detailed coverage of techniques for test generation and testable design of digital electronic circuits/systems. The material covered in the book should be sufficient for a course, or part of a course, in digital circuit testing for senior-level undergraduate and first-year graduate students in Electrical Engineering and Computer Science. The book will also be a valuable resource for engineers working in the industry. This book has four chapters. Chapter 1 deals with various types of faults that may occur in very large scale integration (VLSI)-based digital circuits. Chapter 2 introduces the major concepts of all test generation techniques such as redundancy, fault coverage, sensitization, and backtracking. Chapter 3 introduces the key concepts of testability, followed by some ad hoc design-for-testability rules that can be used to enhance testability of combinational circuits. Chapter 4 deals with test generation and response evaluation techniques used in BIST (built-in self-test) schemes for VLSI chips. Table of Contents: Introduction / Fault Detection in Logic Circuits / Design for Testability / Built-in Self-Test / References

A Comprehensive Delay Model for CMOS CML Circuits

Abstract: MOS-transistor-based current-mode logic (CML)-type (MCML) circuits in high-speed circuit applications often operate as low-swing analog circuits rather than fully switched digital circuits. At these high-speed operations, the effect of the finite input signal slope on the delay of MCML gates significantly increases mainly due to incomplete current steering. Hence, for such cases, the conventional RC delay model which is based on ideal step input assumption fails to track the delay of MCML circuits with errors as high as 40% when a design is optimized for high-speed. In this paper, a comprehensive delay model is proposed that accurately predicts the delay of MCML circuits for all types of operation from low-speed and fully switched to high-speed and low-swing applications by including the input slope effect (ISE) into the conventional RC delay model. Furthermore, the proposed model is extended to multilevel complex logic gates without losing the general RC delay model format. Theoretical results are compared with Spice simulations in a 0.13-mum CMOS technology. Results show that the error in delay of the proposed model is less than 20% for all practical designs. The proposed model is still sufficiently tractable to be use in back-of-envelope calculations that achieve close-to-optimum solutions without running extensive parametric simulations. In addition to the achieved accuracy and preserved simplicity, the proposed model enhances the intuitive understanding of MCML gates that simple RC delay model fails to provide.

Digital circuit to measure and/or correct duty cycles

Abstract: A method, an apparatus, and a computer program are provided to measure and/or correct duty cycles. Duty cycles of various signals, specifically clocking signals, are important. However, measurement of very high frequency signals, off-chip, and in a laboratory environment can be very difficult and present numerous problems. To combat problems associated with making off-chip measurements and adjustments of signal duty cycles, comparisons are made between input signals and divided input signals that allow for easy measurement and adjustment of on-chip signals, including clocking signals.