Showing papers on "Digital electronics published in 2010"

Analysis and Design of Voltage-Controlled Oscillator Based Analog-to-Digital Converter

Abstract: A voltage-controlled oscillator (VCO) based analog-to-digital converter (ADC) is a time-based architecture with a first-order noise-shaping property, which can be implemented using a VCO and digital circuits. This paper analyzes the performance of VCO-based ADCs in the presence of nonidealities such as jitter, nonlinearity, mismatch, and the metastability of D flip-flops. Based on this analysis, design criteria for determining parameters for VCO-based ADCs are described. In addition, a digital calibration technique to enhance the spurious-free dynamic range degraded by the nonlinearity is also introduced. To verify the theoretical analysis, a prototype chip is implemented in a 0.13-?m CMOS process. With a 500-MHz sampling frequency, the prototype achieves a signal-to-noise ratio ranging from 71.8 to 21.3 dB for an input bandwidth of 100 kHz-247 MHz, while dissipating 12.6 mW and occupying an area of 0.078 mm2.

Signal Integrity Design for High-Speed Digital Circuits: Progress and Directions

Abstract: This paper reviews recent progress and future directions of signal integrity design for high-speed digital circuits, focusing on four areas: signal propagation on transmission lines, discontinuity modeling and characterization, measurement techniques, and link-path design and analysis.

Advanced Digital Design with the Verilog HDL

Abstract: Advanced Digital Design with the Verilog HDL, 2e, is ideal for an advanced course in digital design for seniors and first-year graduate students in electrical engineering, computer engineering, and computer science. This book builds on the student's background from a first course in logic design and focuses on developing, verifying, and synthesizing designs of digital circuits. The Verilog language is introduced in an integrated, but selective manner, only as needed to support design examples (includes appendices for additional language details). It addresses the design of several important circuits used in computer systems, digital signal processing, image processing, and other applications.

LEAP: Layout Design through Error-Aware Transistor Positioning for soft-error resilient sequential cell design

Abstract: This paper presents a new layout design principle called LEAP which is an acronym for Layout Design through Error-Aware Transistor Positioning. This principle extends beyond traditional layout techniques, such as node separation, and significantly improves the soft error resilience of digital circuits with negligible performance cost. In this study, we applied the LEAP technique to the Dual Interlocked Storage Cell (DICE) and designed a new sequential element called LEAP-DICE. This element retains the circuit topology and transistor sizing of DICE but has a new layout based on the LEAP principle. Radiation experiments using an 180nm CMOS test chip demonstrate that our LEAP-DICE flip-flop encounters 5X fewer errors on average compared to our reference DICE flip-flop, and 2,000X fewer errors on average compared to a conventional D-flip-flop. Our LEAP-DICE flip-flop imposes negligible power and delay costs and 40% flip-flop-level area costs compared to our reference DICE flip-flop.

European roadmap on superconductive electronics – status and perspectives☆

Abstract: For four decades semiconductor electronics has followed Moore's law: with each generation of integration the circuit features became smaller, more complex and faster. This development is now reaching a wall so that smaller is no longer any faster. The clock rate has saturated at about 3-5 GHz and the parallel processor approach will soon reach its limit. The prime reason for the limitation the semiconductor electronics experiences is not the switching speed of the individual transistor, but its power dissipation and thus heat. Digital superconductive electronics is a circuit- and device-technology that is inherently faster at much less power dissipation than semiconductor electronics. It makes use of superconductors and Josephson junctions as circuit elements, which can provide extremely fast digital devices in a frequency range - dependent on the material - of hundreds of GHz: for example a flip-flop has been demonstrated that operated at 750 GHz. This digital technique is scalable and follows similar design rules as semiconductor devices. Its very low power dissipation of only 0.1 mu W per gate at 100 GHz opens the possibility of three-dimensional integration. Circuits like microprocessors and analogue-to-digital converters for commercial and military applications have been demonstrated. In contrast to semiconductor circuits, the operation of superconducting circuits is based on naturally standardized digital pulses the area of which is exactly the flux quantum Phi(0). The flux quantum is also the natural quantization unit for digital-to-analogue and analogue-to-digital converters. The latter application is so precise, that it is being used as voltage standard and that the physical unit 'Volt' is defined by means of this standard. Apart from its outstanding features for digital electronics, superconductive electronics provides also the most sensitive sensor for magnetic fields: the Superconducting Quantum Interference Device (SQUID). Amongst many other applications SQUIDs are used as sensors for magnetic heart and brain signals in medical applications, as sensor for geological surveying and food-processing and for non-destructive testing. As amplifiers of electrical signals. SQUIDs can nearly reach the theoretical limit given by Quantum Mechanics. A further important field of application is the detection of very weak signals by 'transition-edge' bolo-meters, superconducting nanowire single-photon detectors, and superconductive tunnel junctions. Their application as radiation detectors in a wide frequency range, from microwaves to X-rays is now standard. The very low losses of superconductors have led to commercial microwave filter designs that are now widely used in the USA in base stations for cellular phones and in military communication applications. The number of demonstrated applications is continuously increasing and there is no area in professional electronics, in which superconductive electronics cannot be applied and surpasses the performance of classical devices. Superconductive electronics has to be cooled to very low temperatures. Whereas this was a bottleneck in the past, cooling techniques have made a huge step forward in recent years: very compact systems with high reliability and a wide range of cooling power are available commercially, from microcoolers of match-box size with milli-Watt cooling power to high-reliability coolers of many Watts of cooling power for satellite applications. Superconductive electronics will not replace semiconductor electronics and similar room-temperature techniques in standard applications, but for those applications which require very high speed, low-power consumption, extreme sensitivity or extremely high precision, superconductive electronics is superior to all other available techniques. To strengthen the European competitiveness in superconductor electronics research projects have to be set-up in the following field: - Ultra-sensitive sensing and imaging. - Quantum measurement instrumentation. - Advanced analogue-to-digital converters. - Superconductive electronics technology.

Non-Volatile Magnonic Logic Circuits Engineering

Abstract: We propose a concept of magnetic logic circuits engineering, which takes an advantage of magnetization as a computational state variable and exploits spin waves for information transmission. The circuits consist of magneto-electric cells connected via spin wave buses. We present the result of numerical modeling showing the magneto-electric cell switching as a function of the amplitude as well as the phase of the spin wave. The phase-dependent switching makes it possible to engineer logic gates by exploiting spin wave buses as passive logic elements providing a certain phase-shift to the propagating spin waves. We present a library of logic gates consisting of magneto-electric cells and spin wave buses providing 0 or p phase shifts. The utilization of phases in addition to amplitudes is a powerful tool which let us construct logic circuits with a fewer number of elements than required for CMOS technology. As an example, we present the design of the magnonic Full Adder Circuit comprising only 5 magneto-electric cells. The proposed concept may provide a route to more functional wave-based logic circuitry with capabilities far beyond the limits of the traditional transistor-based approach.

High speed all optical logic gates based on quantum dot semiconductor optical amplifiers

Abstract: A scheme to realize all-optical Boolean logic functions AND, XOR and NOT using semiconductor optical amplifiers with quantum-dot active layers is studied. nonlinear dynamics including carrier heating and spectral hole-burning are taken into account together with the rate equations scheme. Results show with QD excited state and wetting layer serving as dual-reservoir of carriers, as well as the ultra fast carrier relaxation of the QD device, this scheme is suitable for high speed Boolean logic operations. Logic operation can be carried out up to speed of 250 Gb/s.

Device and Circuit Co-Design Robustness Studies in the Subthreshold Logic for Ultralow-Power Applications for 32 nm CMOS

Abstract: Digital circuits operating in a subthreshold region have gained wide interest due to their suitability for applications requiring ultralow power consumption with low-to-medium performance criteria. It has been demonstrated that by appropriately optimizing the devices for subthreshold logic, total energy consumption can be reduced significantly. One of the major concerns for subthreshold circuit design is increased sensitivity to process, voltage, and temperature (PVT) variations. In this paper, we critically study the effect of variations of different device and environmental parameters like gate oxide thickness, channel length, threshold voltage, supply voltage, temperature, and reverse body bias on subthreshold circuit performance for 32 nm bulk CMOS. From the study, we conclude that alternative devices like double-gate silicon-on-insulator (DGSOI) are better candidates in terms of performance, robustness and PVT insensitivity as compared to bulk circuits for both static CMOS and pseudo NMOS logic families. We also study the performance and robustness comparisons of bulk CMOS and DGSOI subthreshold basic logic gates with and without parameter variations and we observe 60-70% improvement in power delay product and roughly 50% better tolerance to PVT variations of DGSOI subthreshold logic circuits compared to bulk CMOS subthreshold circuits at the 32 nm node.

Programmable microcontroller architecture(mixed analog/digital)

Abstract: A microcontroller with a mixed analog/digital architecture including multiple digital programmable blocks and multiple analog programmable blocks in a communication array having a programmable interconnect structure. The single chip design is implemented by integration of programmable digital and analog circuit blocks that are able to communicate with each other. Robust analog and digital blocks that are flash memory programmable can be utilized to realize complex design applications that otherwise would require multiple chips and/or separate applications. The programmable chip architecture includes a novel array having programmable digital blocks that can communicate with programmable analog blocks using a programmable interconnect structure. The programmable analog array contains a complement of Continuous Time (CT) blocks and a complement of Switched Capacitor (SC) blocks that can communicate together. The analog blocks consist of multi-function circuits programmable for one or more different analog functions, and fixed function circuits programmable for a fixed function with variable parameters. The digital blocks include standard multi-function circuits and enhanced circuits having functions not included in the standard digital circuits. The programmable array is programmed by flash memory and programming allows dynamic reconfiguration. That is, “on-the-fly” reconfiguration of the programmable blocks is allowed. The programmable analog array with both Continuous Time analog blocks and Switched Capacitor analog blocks are offered on a single chip along with programmable digital blocks. The programmable interconnect structure provides for communication of input/output data between all analog and digital blocks.

Digital Computation in Subthreshold Region for Ultralow-Power Operation: A Device–Circuit–Architecture Codesign Perspective

Abstract: Ultralow-power dissipation can be achieved by operating digital circuits with scaled supply voltages, albeit with degradation in speed and increased susceptibility to parameter variations. However, operating digital logic and memory circuits in the subthreshold region (supply voltage less than the transistor threshold voltage) for ultralow-power operations requires device, circuit as well as architectural design optimizations, different from the conventional superthreshold design. This paper analyzes such optimizations from energy dissipation point of view and shows that it is feasible to achieve robust operation of ultralow-voltage systems. Operation with power supply as low as 60 mV is demonstrated. Techniques to reduce the impact of process variations on subthreshold circuits are also discussed. In addition, it is shown that subthreshold leakage current can be useful for other applications like thermal sensors.

Optimization of reversible sequential circuits

Abstract: In recent years reversible logic has been considered as an important issue for designing low power digital circuits. It has voluminous applications in the present rising nanotechnology such as DNA computing, Quantum Computing, low power VLSI and quantum dot automata. In this paper we have proposed optimized design of reversible sequential circuits in terms of number of gates, delay and hardware complexity. We have designed the latches with a new reversible gate and reduced the required number of gates, garbage outputs, and delay and hardware complexity. As the number of gates and garbage outputs increase the complexity of reversible circuits, this design will significantly enhance the performance. We have proposed reversible D-latch and JK latch which are better than the existing designs available in literature.

100 GHz demonstrations based on the single-flux-quantum cell library for the 10 kA/cm 2 Nb multi-layer process

Abstract: A single flux quantum (SFQ) logic cell library has been developed for the 10kA/cm 2 Nb multi-layer fabrication process to efficiently design large-scale SFQ digital circuits. In the new cell library, the critical current density of Josephson junctions is increased from 2.5 kA/cm 2 to 10 kA/cm 2 compared to our conventional cell library, and the McCumber-Stwart parameter of each Josephson junction is increased to 2 in order to increase the circuit operation speed. More than 300 cells have been designed, including fundamental logic cells and wiring cells for passive interconnects. We have measured all cells and confirmed they stably operate with wide operating margins. On-chip high-speed test of the toggle flip-flop (TFF) cell has been performed by measuring the input and output voltages. The TFF cell at the input frequency of up to 400 GHz was confirmed to operate correctly. Also, several fundamental digital circuits, a 4-bit concurrent-flow shift register and a bit-serial adder have been designed using the new cell library, and the correct operations of the circuits have been demonstrated at high clock frequencies of more than 100 GHz.

Experimental Demonstration of Fanout for Nanomagnetic Logic

Abstract: Nanomagnet logic (NML) shows great promise as an alternative to conventional digital architectures. We present the first experimental demonstration of fanout using magnetizations of nanomagnets in the NML scheme. Specifically, we show magnetic force microscopy images of functioning fanout circuits.

Software Assisted Digital RF Processor (DRP™) for Single-Chip GSM Radio in 90 nm CMOS

Abstract: This paper proposes and describes a new software and application programming interface view of an RF transceiver. It demonstrates benefits of using highly programmable digital control logic in an RF wireless system realized in a digital nanoscale CMOS process technology. It also describes a microprocessor architecture design in Digital RF Processor (DRPTM) and how it controls calibration and compensation for process, temperature and voltage variations of the analog and RF circuits to meet the required RF performance. A few calibration examples to reduce a DCO bias current and improve device reliability, as well as to optimize transmit modulation and receive performance, are given. The presented circuits and techniques have enabled successful implementation of a commercial single-chip GSM radio in 90 nm CMOS.

Efficient Variability-Aware NBTI and Hot Carrier Circuit Reliability Analysis

Abstract: This paper discusses an efficient method to analyze the spatial and temporal reliability of analog and digital circuits. First, a SPICE-based reliability simulator with automatic step-size control is proposed. Both hot carrier degradation and negative bias temperature instability are included in the simulator. Next, a method to analyze the interaction between process variability effects and circuit aging is introduced. This method is based on a screening experimental design (DoE) succeeded by a set of regression DoEs, resulting in a good speed-accuracy tradeoff with a nearly linear complexity for all circuits under test. Finally, based on the DoE analysis, a circuit response surface model (RSM) is derived. The RSM is used for further circuit reliability analysis such as circuit weak spot detection and yield calculation as a function of circuit lifetime. The proposed method is validated over a broad range of both analog and digital circuits. Yield simulation time is reduced with up to three orders of magnitude, when compared to standard Monte Carlo-based techniques and while still maintaining simulation accuracy.

Ultralow-Power Operation in Subthreshold Regimes Applying Clockless Logic

Abstract: Energy performance requirements are causing designers of next-generation systems to explore approaches to lowest possible power consumption Subthreshold operation is being examined to stretch low-power circuit designs beyond the normal modes of operation, with the potential for large energy savings Some of the challenges to be overcome, like 10-100× performance penalties, are being addressed by research into parallelism However, the uncertainty in timing generated by operating in subthreshold represents a major challenge to overcome In this paper, first, we will introduce some background information on digital logic subthreshold operation, then provide some background on clockless logic design approaches giving a brief overview of some of the characteristics of the different design styles and focusing on NULL convention logic Next, we will examine the application of that clockless logic approach to a military system, reviewing the background of the experiment, factors considered in the comparison, and then summarizing the results of the comparisons Finally, an overview of additional research and development that will be needed to make the technique available to subthreshold designers is presented

A maximally-digital radio receiver front-end

Abstract: Previous work [1,2] has demonstrated the feasibility of a drastic reduction of the analog circuits content in radio transmitters and synthesizers, in favour of more digital circuits. But for radio receivers, a major amount of analog circuitry is still required [1,3]. This paper demonstrates the feasibility of further reducing the analog circuit content of a radio receiver, while maintaining acceptable performance. The circuit offers the main advantages of a digital design: after adding one (small) macroblock to a digital standard-cell library, the whole receiver can be described in an RTL language and can be realised with a standard digital design methodology. Porting or scaling to another silicon technology becomes relatively easy.

Entropy extraction in metastability-based TRNG

Abstract: True Random Number Generators (TRNG) implemented in deep sub micron (DSM) technologies become biased in bit generation due to process variations and fluctuations in operating conditions. A variety of mechanisms ranging from analog and digital circuit techniques to algorithmic post-processing can be employed to remove bias. In this work we compare the effectiveness of digital post-processing using the XOR function and Von Neumann Corrector with circuit calibration technique for a meta-stability based reference TRNG design. The energy consumption per bit is used as the metric for comparison of the different techniques. The results indicate that the calibration technique is effective for 12% larger process variation than the XOR function and extracts entropy comparable to the Von Neumann Corrector at 56% lesser energy/bit. The analysis thereby demonstrates that circuit calibration provides an efficient tradeoff between entropy and energy/bit for removing bias in lightweight TRNG.

High-Efficiency Soft-Error-Tolerant Digital Signal Processing Using Fine-Grain Subword-Detection Processing

Abstract: The soft error problem in digital circuits is becoming increasingly important as the IC fabrication technology progresses from the deep submicrometer scale to the nanometer scale. This paper proposes a subword-detection processing (SDP) technique and a fine-grain soft-error-tolerance (FGSET) architecture to improve the performance of the digital signal processing circuit. In the SDP technique, the logic masking property of the soft error in the combinational circuit is utilized to mask the single-event upset (SEU) caused by disturbing particles in the inactive area. To further improve the performance, the masked portion of the datapath can be used as the estimation redundancy in the algorithmic softerror-tolerance (ASET) technique. This technique is called subword-detection and redundant processing (SDRP). In the FGSET architecture, the soft error in each processing element (fine grain) can be recovered by the arithmetic datapath-level ASET technique. Analysis of the fast Fourier transform processor example shows that the proposed FGSET architecture can improve the performance of the coarse-grain SET (CGSET) by 8.5 dB. The low-cost SDP technique (1.03x) yields a noise reduction of 5.3 dB over the CGSET approach (1.40x), while the efficient SDRP I (1.57x) and SDRP II (1.88x) techniques outperform the CGSET approach by 24.5 and 30.5 dB, respectively.

An ECG-on-Chip for Wearable Cardiac Monitoring Devices

Abstract: This paper describes a highly integrated, low power chip solution for ECG signal processing in wearable devices. The chip contains an instrumentation amplifier with programmable gain, a band-pass filter, a 12-bit SAR ADC, a novel QRS detector, 8K on-chip SRAM, and relevant control circuitry and CPU interfaces. The analog front end circuits accurately senses and digitizes the raw ECG signal, which is then filtered to extract the QRS. The sampling frequency used is 256 Hz. ECG samples are buffered locally on an asynchronous FIFO and is read out using a faster clock, as and when it is required by the host CPU via an SPI interface. The chip was designed and implemented in 0.35µm standard CMOS process. The analog core operates at 1V while the digital circuits and SRAM operate at 3.3V. The chip total core area is 5.74 mm2 and consumes 9.6µW. Small size and low power consumption make this design suitable for usage in wearable heart monitoring devices.

Digital Logic Implementation in Memristor-Based Crossbars - A Tutorial

Abstract: A memristor is a passive electronic device that was proposed and described by Leon Chua in 1971. The first practical implementation has been realized by Stan Williams’ group at HP Labs in 2008. The goal of this paper is to give the reader a brief introduction to the possibilities of logic design using memristors. It paper is intended as a tutorial on how to use memristor crossbars for logic design and is a consolidation of various recent publications.

A comprehensive approach to modeling, characterizing and optimizing for metastability in FPGAs

Abstract: Metastability is a phenomenon that can cause system failures in digital circuits. It may occur whenever signals are being transmitted across asynchronous or unrelated clock domains. The impact of metastability is increasing as process geometries shrink and supply voltages drop faster than transistor Vts. FPGA technologies are significantly affected since leading edge FPGAs are amongst the first devices to adopt the most recent process nodes. In this paper, we present a comprehensive suite of techniques for modeling, characterizing and optimizing metastability effects in FPGAs. We first discuss a theoretical model of metastability, and verify the predictions using both circuit level simulations and board measurements. Next we show how designers have traditionally dealt with metastability problems and contrast that with the automatic CAD algorithms described in this paper that both analyze and optimize metastability-related issues. Through our detailed experimental results, we show that we can improve the metastability characteristics of a large suite of industrial benchmarks by an average of 268,000 times with our optimization techniques.

Design of Asynchronous Circuits for High Soft Error Tolerance in Deep Submicrometer CMOS Circuits

Abstract: As the devices are scaling down, the combinational logic will become susceptible to soft errors. The conventional soft error tolerant methods for soft errors on combinational logic do not provide enough high soft error tolerant capability with reasonably small performance penalty. This paper investigates the feasibility of designing quasi-delay insensitive (QDI) asynchronous circuits for high soft error tolerance. We analyze the behavior of null convention logic (NCL) circuits in the presence of particle strikes, and propose an asynchronous pipeline for soft-error correction and a novel technique to improve the robustness of threshold gates, which are basic components in NCL, against particle strikes by using Schmitt trigger circuit and resizing the feedback transistor. Experimental results show that the proposed threshold gates do not generate soft errors under the strike of a particle within a certain energy range if a proper transistor size is applied. The penalties, such as delay and power consumption, are also presented.

Fortifying analog models with equivalence checking and coverage analysis

Abstract: As analog and digital circuits have become more intertwined, we need to create a validation approach that handles both circuit types gracefully. This paper proposes a model-first approach, where one creates functional models of the analog blocks that will work in a HDL simulator, and then uses these models in the same way as HDL models are used for other standard cells: they are used in the full system validation, and the underlying implementations are validated to ensure they meet this specification. While creating functional models for the analog blocks might seem difficult, almost all analog blocks can be modeled as linear systems and we use this property to help create the required functional model.

ABRM: Adaptive $ \beta$ -Ratio Modulation for Process-Tolerant Ultradynamic Voltage Scaling

Abstract: Subthreshold operation of digital circuits has emerged as a promising approach to achieve ultralow power dissipation. However, extensive application of subthreshold logic is limited due to low performance and high susceptibility to process variation (PV). This paper proposes a PV-tolerant ultradynamic voltage scaling (UDVS) system where performance requirements dictate whether the devices will work in the subthreshold or superthreshold region. Due to different mechanisms of current conduction, it is necessary to use different P/N ratios for different regions of operation to improve circuit robustness, performance, and power. With an analytical model of circuit robustness, we present an adaptive body-biasing technique to dynamically adjust the s-ratio depending on the operating region. Measurements show that our methodology improves the dynamic range of operation the circuits-from 1.2 V all the way down to 85 mV consuming 40 nW (at 85 mV) of power for an 8 t 8 finite-impulse response filter fabricated in a 0.13-?m technology, and can salvage circuits which otherwise would fail to operate due to device mismatches and skewed P/N ratios.

Method and digital circuit for recovering a clock and data from an input signal using a digital frequency detection

Abstract: In a particular embodiment, a digital circuit includes a frequency detection circuit operative to compare information related to transitions between sequential samples of a received signal. The frequency detection circuit is further operative to generate a control signal to reduce a sampling rate of the received signal in response to a predetermined number of the sequential samples having a same value. The digital circuit also includes a digital phase detector operative to provide the information related to the transitions between sequential samples to the frequency detection circuit.

All-Digital Circuits for Measurement of Spatial Variation in Digital Circuits

Abstract: Increased variation in CMOS processes due to scaling results in greater reliance on accurate variation models in developing circuit methods to mitigate variation. This paper investigates spatial variation in digital circuit performance: we describe a test-chip in 90 nm CMOS containing all-digital measurement circuits capable of extracting accurate variation data. Specifically, we use replicated 64-bit Kogge-Stone adders, ring oscillators (ROs) of varying gate type and stage length and an all-digital, sub-picosecond resolution delay measurement circuit to provide this data. Measurement data from the test-chips indicate that 1) relative variation is significantly larger in low-voltage domains, 2) within-die variation is spatially uncorrelated, and 3) die-to-die (or global) variation is strongly correlated, but degrades toward uncorrelated as the power-supply voltage is lowered. Lastly, extended analysis of the data reveals that systematic effects such as layout pattern dependencies or circuit structure can be misinterpreted as random but spatially-correlated variation. This suggests that circuit designers will reap more benefit from design tools capable of modeling systematic, position-dependent variation rather than spatially correlated, distance-dependent variation.

Digital Circuit Realization of Piecewise-Affine Functions With Nonuniform Resolution: Theory and FPGA Implementation

Abstract: This brief proposes a digital circuit architecture implementing a class of continuous piecewise-affine (PWA) functions. The work rests on a previous architecture realizing PWA functions with uniform resolution. By using PWA mapping that can be implemented through a few simple functional blocks, it is possible to extend the representation capabilities of the architecture to PWA functions with nonuniform resolution. After defining the mapping and the corresponding functional blocks, the proposed architecture is implemented in a field-programmable gate array, and a simple example is shown.

Fuel gauging system utilizing a digital fuel gauging probe

Abstract: A fluid measurement system utilizes one or more digital probes that communicate over a digital bus to a fluid gauging computer. The digital probes incorporate a capacitance to digital circuit that converts probe capacitance to a digital value. The digital value is communicated to the fuel gauging computer via a data bus.