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Showing papers on "Digital electronics published in 2011"


Journal ArticleDOI
03 Jun 2011-Science
TL;DR: This work experimentally demonstrated several digital logic circuits, culminating in a four-bit square-root circuit that comprises 130 DNA strands, which enables fast and reliable function in large circuits with roughly constant switching time and linear signal propagation delays.
Abstract: To construct sophisticated biochemical circuits from scratch, one needs to understand how simple the building blocks can be and how robustly such circuits can scale up. Using a simple DNA reaction mechanism based on a reversible strand displacement process, we experimentally demonstrated several digital logic circuits, culminating in a four-bit square-root circuit that comprises 130 DNA strands. These multilayer circuits include thresholding and catalysis within every logical operation to perform digital signal restoration, which enables fast and reliable function in large circuits with roughly constant switching time and linear signal propagation delays. The design naturally incorporates other crucial elements for large-scale circuitry, such as general debugging tools, parallel circuit preparation, and an abstraction hierarchy supported by an automated circuit compiler.

1,249 citations


Journal ArticleDOI
10 Nov 2011-ACS Nano
TL;DR: This report reports on the first integrated circuit based on a two-dimensional semiconductor MoS(2) transistors, capable of operating as inverters, converting logical "1" into logical "0", with room-temperature voltage gain higher than 1, making them suitable for incorporation into digital circuits.
Abstract: Logic circuits and the ability to amplify electrical signals form the functional backbone of electronics along with the possibility to integrate multiple elements on the same chip. The miniaturization of electronic circuits is expected to reach fundamental limits in the near future. Two-dimensional materials such as single-layer MoS2 represent the ultimate limit of miniaturization in the vertical dimension, are interesting as building blocks of low-power nanoelectronic devices, and are suitable for integration due to their planar geometry. Because they are less than 1 nm thin, 2D materials in transistors could also lead to reduced short channel effects and result in fabrication of smaller and more power-efficient transistors. Here, we report on the first integrated circuit based on a two-dimensional semiconductor MoS2. Our integrated circuits are capable of operating as inverters, converting logical “1” into logical “0”, with room-temperature voltage gain higher than 1, making them suitable for incorporat...

1,244 citations


Journal ArticleDOI
TL;DR: A novel design technique for ternary logic gates based onCNTFETs is proposed and compared with the existing resistive-load CNTFET logic gate designs, which provides an excellent speed and power consumption characteristics in datapath circuit such as full adder and multiplier.
Abstract: This paper presents a novel design of ternary logic gates using carbon nanotube (CNT) FETs (CNTFETs). Ternary logic is a promising alternative to the conventional binary logic design technique, since it is possible to accomplish simplicity and energy efficiency in modern digital design due to the reduced circuit overhead such as interconnects and chip area. A resistive-load CNTFET-based ternary logic design has been proposed to implement ternary logic based on CNTFET. In this paper, a novel design technique for ternary logic gates based on CNTFETs is proposed and compared with the existing resistive-load CNTFET logic gate designs. Especially, the proposed ternary logic gate design technique combined with the conventional binary logic gate design technique provides an excellent speed and power consumption characteristics in datapath circuit such as full adder and multiplier. Extensive simulation results using SPICE are reported to show that the proposed ternary logic gates consume significantly lower power and delay than the previous resistive-load CNTFET gates implementations. In realistic circuit application, the utilization of the proposed ternary gates combined with binary gates results in over 90% reductions in terms of the power delay product.

461 citations


Journal ArticleDOI
TL;DR: In this paper, a new superconducting digital technology called reciprocal quantum logic (RQL) was developed, which uses ac power carried on a transmission line as a clock, and combines the high speed and low power signal levels of single-flux-quantum signals with the design methodology of semiconductor digital logic, including low static power dissipation, low latency combinational logic, and efficient device count.
Abstract: We have developed a new superconducting digital technology, Reciprocal Quantum Logic, that uses ac power carried on a transmission line, which also serves as a clock. Using simple experiments, we have demonstrated zero static power dissipation, thermally limited dynamic power dissipation, high clock stability, high operating margins, and a low bit-error rate. These features indicate that the technology is scalable to far more complex circuits at a significant level of integration. On the system level, Reciprocal Quantum Logic combines the high speed and low-power signal levels of single-flux-quantum signals with the design methodology of semiconductor digital logic, including low static power dissipation, low latency combinational logic, and efficient device count.

311 citations


Journal ArticleDOI
TL;DR: A reconfigurable optical directed logic architecture that offers several significant improvements over the original directed logic presented by Hardy and Shamir is presented.
Abstract: We present a reconfigurable optical directed logic architecture that offers several significant improvements over the original directed logic presented by Hardy and Shamir. Specific embodiments of on-chip, waveguided, large-scale-integrated, cellular optical directed logic fabrics are proposed and analyzed. Five important logic functions are presented as examples to show that the same switch fabric can be reconfigured to perform different logic functions.

181 citations


Journal ArticleDOI
TL;DR: In this article, a coupled magnetodynamics/spin-transport model for all spin logic (ASL) devices is presented, which is based on established physics and is benchmarked against available experimental data.
Abstract: A recent proposal called all spin logic (ASL) proposes to store information in nanomagnets that communicate with spin currents in order to construct spin based digital circuits. We present a coupled magnetodynamics/spin-transport model for ASL devices that is based on established physics and is benchmarked against available experimental data. This model is used to show the linear dependence of switching energy and quadratic dependence of energy-delay of ASL devices on the number of Bohr magnetons comprising a nanomagnet. A scaling scheme that could lower the energy-delay of spin-torque switching while maintaining thermal stability is discussed.

129 citations


Journal ArticleDOI
TL;DR: A new timing belt clocking scheme is introduced and new circuits based on nSQUID gates with fundamentally low energy dissipation and the ability to operate in irreversible and reversible modes are presented.
Abstract: We continue to develop a new Superconductor Flux Logic (SFL) family based on nSQUID gates with fundamentally low energy dissipation and the ability to operate in irreversible and reversible modes. Prospective computers utilizing the new gates can keep conventional logically irreversible architectures. In this case the energy dissipation is limited by fundamental thermodynamic laws and could be as low as a few kBT s per logic operation. Highly exotic and less practical logically and physically reversible circuit architectures are more attractive for us because they enable a reduction of the specific energy dissipation well below the thermodynamic threshold kBTln2. The reversible option is of interest to us because we can then experimentally demonstrate that all technical mechanisms of the energy dissipation could be cut below the fundamental thermodynamic limit. In other words, we like to set the energy dissipation record for all conventional digital technologies that (if measured in kBT ) is about one million times below the best figures achieved in commercially available semiconductor circuits. Besides, we believe that diving below the thermodynamic threshold would have impressive scientific and philosophical impacts. In the paper we introduce a new timing belt clocking scheme and present new circuits. While we still work with test circuits, some of them contain two 8-stage shift registers, one with direct and the other with inverted outputs. The energy dissipation per nSQUID gate per bit measured at 4 K temperature is already below the thermodynamic threshold. We are confident that we passed through the critical phase of the project and we simply need more time to make more sophisticated circuits. The extremely low energy dissipation converts our circuits into a natural candidate to support circuitry for any sensors operating at milli-Kelvin temperatures.

114 citations


Journal ArticleDOI
TL;DR: Dual-gate organic transistor technology is used to increase the robustness of digital circuits as illustrated by higher inverter gains and noise margins as well as Functional 99-stage ring oscillators with 2.27 μs stage delays and 64 bit organic RFID transponder chips, operating at a data rate of 4.3 kb/s.
Abstract: Dual-gate organic transistor technology is used to increase the robustness of digital circuits as illustrated by higher inverter gains and noise margins. The additional gate in the technology functions as a VT-control gate. Both zero-VGS-load and diode-load logic are investigated. The noise margin of zero- VGS-load inverter increases from 1.15 V (single gate) to 2.8 V (dual gate) at 20 V supply voltage. Diode-load logic inverters show an improvement in noise margin from ~0 V to 0.7 V for single gate and dual gate inverters, respectively. These values can be increased significantly by optimizing the inverter topologies. As a result of this optimization, noise margins larger than 6 V for zero- VGS-load logic and 1.4 V for diode-load logic are obtained. Functional 99-stage ring oscillators with 2.27 μs stage delays and 64 bit organic RFID transponder chips, operating at a data rate of 4.3 kb/s, have been manufactured.

109 citations


Journal ArticleDOI
TL;DR: Proposed logic gates have the potential to be key components for an optical packet switching system due to their small feature sizes and low power consumption.

100 citations


Journal ArticleDOI
TL;DR: In this article, the spin-dependent transport property of zigzag graphene nanoribbons was studied using nonequilibrium Green's function method and density functional theory, and a complete set of all-carbon spin logic gates, in which the spinpolarized current can be manipulated by the source-drain voltage and magnetic configuration of the electrodes.
Abstract: Logic operation is the key of digital electronics and spintronics. Based on spin-dependent transport property of zigzag graphene nanoribbons studied using nonequilibrium Green’s function method and density functional theory, we propose a complete set of all-carbon spin logic gates, in which the spin-polarized current can be manipulated by the source-drain voltage and magnetic configuration of the electrodes. These logic gates allow further designs of complex spin logic operations and pave the way for full implementation of spintronics computing devices.

64 citations


Journal ArticleDOI
TL;DR: In this paper, the analog and digital circuits implemented in a dual threshold voltage p-channel organic technology are presented, which is compatible with large area and mechanically flexible substrates due to its low processing temperature (≤ 95°C) and scalable patterning techniques.
Abstract: Analog & digital circuits implemented in a dual threshold voltage (VT) p-channel organic technology are presented. The dual VT organic technology is compatible with large-area and mechanically flexible substrates due to its low processing temperature (≤ 95°C) and scalable patterning techniques. We demonstrate the first analog & digital organic integrated circuits produced by a dual-gate metal process. The analog circuits are powered by a 5-V supply and include a differential amplifier and a two-stage uncompensated operational amplifier (op-amp). A dynamic comparator is measured to have an input offset voltage of 200 mV and latching time of 119 ms. Both the comparator and the op-amp dissipate 5 nW or less. Area-minimized digital logic is presented. Inverters powered by a 3-V supply were measured to have positive noise margins and consumed picowatts of power. An 11-stage ring oscillator, also powered by a 3-V supply, swings near rail to rail at 1.7 Hz. These results demonstrate dual threshold voltage process feasibility for large-area flexible mixed-signal organic integrated circuits.

Proceedings ArticleDOI
23 Sep 2011
TL;DR: The output of the digital circuit is proved to be chaotic by calculating the output time series maximum Lyapunov exponent and a new post processing technique is introduced to improve the distribution and statistical properties of the generated data.
Abstract: In this paper, we present a fully digital differential chaos based random number generator. The output of the digital circuit is proved to be chaotic by calculating the output time series maximum Lyapunov exponent. We introduce a new post processing technique to improve the distribution and statistical properties of the generated data. The post-processed output passes the NIST Sp. 800-22 statistical tests. The system is written in Verilog VHDL and realized on Xilinx Virtex® FPGA. The generator can fit into a very small area and have a maximum throughput of 2.1 Gb/s.

Journal ArticleDOI
TL;DR: A formal verification algorithm is utilized to reduce the fitness evaluation time for evolutionary post-synthesis optimization in evolvable hardware and it is demonstrated that the method can optimize digital circuits of tens of inputs and thousands of gates.
Abstract: We propose to utilize a formal verification algorithm to reduce the fitness evaluation time for evolutionary post-synthesis optimization in evolvable hardware. The proposed method assumes that a fully functional digital circuit is available. A post-synthesis optimization is then conducted using Cartesian Genetic Programming (CGP) which utilizes a satisfiability problem solver to decide whether a candidate solution is functionally correct or not. It is demonstrated that the method can optimize digital circuits of tens of inputs and thousands of gates. Furthermore, the number of gates was reduced for the LGSynth93 benchmark circuits by 37.8% on average with respect to results of the conventional SIS tool.

Journal ArticleDOI
TL;DR: A simplified technology-independent fault model, the single transient fault (STF), is proposed for efficiently estimating the error probabilities associated with individual nodes in both combinational and sequential logic.
Abstract: Transient or soft errors caused by various environmental effects are a growing concern in micro and nanoelectronics. We present a general framework for modeling and mitigating the logical effects of such errors in digital circuits. We observe that some errors have time-bounded effects; the system's output is corrupted for a few clock cycles, after which it recovers automatically. Since such erroneous behavior can be tolerated by some applications, i.e., it is noncritical at the system level, we define the critical soft error rate (CSER) as a more realistic alternative to the conventional SER measure. A simplified technology-independent fault model, the single transient fault (STF), is proposed for efficiently estimating the error probabilities associated with individual nodes in both combinational and sequential logic. STFs can be used to compute various other useful metrics for the faults and errors of interest, and the required computations can leverage the large body of existing methods and tools designed for (permanent) stuck-at faults. As an application of the proposed methodology, we introduce a systematic strategy for hardening logic circuits against transient faults. The goal is to achieve a desired level of CSER at minimum cost by selecting a subset of nodes for hardening against STFs. Exact and approximate algorithms to solve the node selection problem are presented. The effectiveness of this approach is demonstrated by experiments with the ISCAS-85 and -89 benchmark suites, as well as some large (multimillion-gate) industrial circuits.

Book ChapterDOI
01 Jan 2011
TL;DR: It will be shown that functional decomposition method allows for very flexible synthesis of the designed system onto heterogeneous structures of modern FPGAs composed of logic cells and EMBs.
Abstract: The paper presents logic synthesis method targeted at FPGA architectures with specialized embedded memory blocks (EMBs). Existing methods do not ensure effective utilization of the possibilities provided by such modules. The problem of efficient mapping of combinational and sequential parts of design can be solved using decomposition algorithms. The main question of this paper is the application of decomposition based methods for efficient utilization of modern FPGAs. It will be shown that functional decomposition method allows for very flexible synthesis of the designed system onto heterogeneous structures of modern FPGAs composed of logic cells and EMBs. Finally we present results of the experiments, which evidently show, that the application of functional decomposition algorithms in the implementation of typical signal and information processing systems greatly influences the performance of resultant digital circuits.

Journal ArticleDOI
TL;DR: In this paper, a 10-nm Dual-Material Surrounded Gate MOSFETs (DMSG) was proposed and simulated for nanoscale digital circuit applications and the sub-threshold electrical properties such as subthreshold current-voltage characteristics, sub-reshold swing factor, threshold voltage and drain induced barrier lowering (DIBL) of the device have been ascertained and mathematical models have been developed.
Abstract: In this paper, we have proposed and simulated a new 10-nm Dual-Material Surrounded Gate MOSFETs (DMSG) MOSFETs for nanoscale digital circuit applications. The subthreshold electrical properties such as subthreshold current–voltage characteristics, subthreshold swing factor, threshold voltage and drain induced barrier lowering (DIBL) of the device have been ascertained and mathematical models have been developed. It has been observed that the DM design can effectively suppress short-channel effects as compared to single material gate structure. The proposed analytical expressions are used to formulate the objective functions, which are the pre-requisite of genetic algorithm computation. The problem is then presented as a multi-objective optimization one where the subthreshold electrical parameters are considered simultaneously. Therefore, the proposed technique is used to search of the optimal electrical and geometrical parameters to obtain better electrical performance of the 10-nm-scale transistor. These characteristics make the optimized 10-nm transistors potentially suitable for deep nanoscale logic and memory applications.

Proceedings ArticleDOI
01 May 2011
TL;DR: An adaptive error-prediction flip-flop architecture with built-in aging sensor is proposed, performing on-line monitoring of long-term performance degradation of CMOS digital systems, and the impact of aging degradation and/or PVT variations on the sensor enhance error prediction.
Abstract: This paper presents a new approach on aging sensors for synchronous digital circuits. An adaptive error-prediction flip-flop architecture with built-in aging sensor is proposed, performing on-line monitoring of long-term performance degradation of CMOS digital systems. The main advantage is that the sensor's performance degradation works in favor of the predictive error detection. The sensor is out of the signal path. Performance error prediction is implemented by the detection of late transitions at flip-flop data input, caused by aging (namely, due to NBTI), or to physical defects activated by long lifetime operation. Such errors must not occur in safety-critical systems (automotive, health, space). A sensor insertion algorithm is also proposed, to selectively insert them in key locations in the design. Sensors can be always active or at pre-defined states. Simulation results are presented for a balanced pipeline multiplier in 65 nm CMOS technology, using Berkeley Predictive Technology Models (PTM). It is shown that the impact of aging degradation and/or PVT (Process, power supply Voltage and Temperature) variations on the sensor enhance error prediction.

Journal ArticleDOI
TL;DR: In this article, the authors present an assessment of different approaches for reducing the static power consumption by investigating the potential of inductive bias distribution networks as well as reduced critical currents and inductive biasing.
Abstract: Rapid single flux quantum (RSFQ) electronics is based on the Josephson junction as an active switching element. In standard RSFQ circuits its switching energy is much lower than the static power consumption caused by the resistive current distribution network. Due to this thermal heating of the chip, the maximum number of junctions on a single chip is limited to about 1 million. The frequency-dependent contribution to power dissipation from junction switchings is only about 2 percent of the static one. This fact limits the direct construction of VLSI systems for high-performance computing as well as small-scale circuit applications in the vicinity of ultra-sensitive detectors or even quantum circuits. We present an assessment of different approaches for reducing the static power consumption by investigating the potential of inductive bias distribution networks as well as reduced critical currents. We analyse the operation stability of simple digital circuits with 5 times smaller critical currents at 4.2 K. The combination of the reduced critical currents and inductive biasing can provide digital superconductive circuits with significantly reduced static power consumption.

Patent
26 Aug 2011
TL;DR: In this paper, a semiconductor integrated circuit includes a first semiconductor substrate in which a part of an analog circuit is formed between the analog circuit and a digital circuit, and a substrate connection portion which connects the first and second semiconductor substrates to each other.
Abstract: A semiconductor integrated circuit includes a first semiconductor substrate in which a part of an analog circuit is formed between the analog circuit and a digital circuit which subjects an analog output signal output from the analog circuit to digital conversion; a second semiconductor substrate in which the remaining part of the analog circuit and the digital circuit are formed; and a substrate connection portion which connects the first and second semiconductor substrates to each other. The substrate connection portion transmits an analog signal which is generated by a part of the analog circuit of the first semiconductor substrate to the second semiconductor substrate.

Journal ArticleDOI
TL;DR: A formal model uses a fixed bound in time and exploits fault detection circuitry to cope with the complexity of the underlying sequential equivalence check and returns a lower and an upper bound on the robustness of a digital circuit with respect to transient faults.
Abstract: Continuously shrinking feature sizes result in an increasing susceptibility of circuits to transient faults, e.g., due to environmental radiation. Approaches to implement fault tolerance are known. But assessing the fault tolerance of a given implementation is a hard verification problem. Here, we propose the use of formal methods to assess the robustness of a digital circuit with respect to transient faults. Our formal model uses a fixed bound in time and exploits fault detection circuitry to cope with the complexity of the underlying sequential equivalence check. As a result, a lower and an upper bound on the robustness are returned together with vulnerable components. The underlying algorithm and techniques to improve the efficiency are presented. In experiments, we evaluate the method on circuits with different fault detection mechanisms.

Journal ArticleDOI
TL;DR: This article analyzes and compares nanomagnetic circuits based on full NCL, mixed Boolean-NCL, and fully Boolean logic, and discusses the advantages of these logics, but also the issues they raise.
Abstract: In the years to come new solutions will be required to overcome the limitations of scaled CMOS technology. One approach is to adopt Nano-Magnetic Logic Circuits, highly appealing for their extremely reduced power consumption. Despite the interesting nature of this approach, many problems arise when this technology is considered for real designs. The wire is the most critical of these problems from the circuit implementation point of view. It works as a pipelined interconnection, and its delay in terms of clock cycles depends on its length. Serious complications arise at the design phase, both in terms of synthesis and of physical design.One possible solution is the use of a delay insensitive asynchronous logic, Null Convention Logic (NCLTM). Nevertheless its use has many negative consequences in terms of area occupation and speed loss with respect to a Boolean version. In this article we analyze and compare different solutions: nanomagnetic circuits based on full NCL, mixed Boolean-NCL, and fully Boolean logic. We discuss the advantages of these logics, but also the issues they raise. In particular we analyze feedback signals, which, due to their intrinsic pipelined nature, cause errors that still have not found a solution in the literature. The innovative arrangement we propose solves most of the problems and thus soundly increases the knowledge of this technology. The analysis is performed using a VHDL behavioral model we developed and a microprocessor we designed based on this model, as a sound and realistic test bench.

Journal ArticleDOI
TL;DR: The proposed approach is used to find the optimal electrical and dimensional transistor parameters in order to obtain and explore the better transistor performances for analog and digital CMOS-based circuit applications.

Proceedings ArticleDOI
07 Nov 2011
TL;DR: A simple, fast, and very efficient synthesis algorithm to improve the delay after technology mapping that scales to large designs and is implemented in a publicly-available technology mapper.
Abstract: Reducing delay of a digital circuit is an important topic in logic synthesis for standard cells and LUT-based FPGAs. This paper presents a simple, fast, and very efficient synthesis algorithm to improve the delay after technology mapping. The algorithm scales to large designs and is implemented in a publicly-available technology mapper. The code is available online. Experimental results on industrial designs show that the method can improve delay after standard cell mapping by 30% with the increase in area 2.4%, or by 41% with the increase in area by 3.9%, on top of a high-effort synthesis and mapping flow. In a separate experiment, the algorithm was used as part of a complete industrial standard cell design flow, leading to improvements in area and delay after place-and-route. In yet another experiment, the algorithm was applied before FPGA mapping into 4-LUTs, resulting in 16% logic level reduction at the cost of 9% area increase on top of a high-effort mapping.

Book
28 Nov 2011
TL;DR: This paper discusses the design and Fabrication options for implementation of VLSI Testing Fault Models, and the design methods used for Verilog HDL/SystemVerilog and Sequential Logic Modules, and their applications.
Abstract: Introduction MOS Transistors as Switches VLSI Design and Fabrication Implementation Options of Digital Systems Fundamentals of MOS Transistors Semiconductor Fundamentals The pn Junction MOS Transistor Theory Advanced Features of MOS Transistors SPICE and Modeling Fabrication of CMOS ICs Basic Processes Materials and Their Applications Process Integration Enhancements of CMOS Processes and Devices Layout Designs Layout Design Rules CMOS Latch-Up and Prevention Layout Designs Layout Methods for Complex Logic Gates Delay Models and Path-Delay Optimization Resistance and Capacitance of MOS Transistors Propagation Delays and Delay Models Path-Delay Optimization Power Dissipation and Low-Power Designs Power Dissipation Principles of Low-Power Logic Designs Low-Power Logic Architectures Power Management Static Logic Circuits Basic Static Logic Circuits Single-Rail Logic Circuits Dual-Rail Logic Circuits Dynamic Logic Circuits Introduction to Dynamic Logic Nonideal Effects of Dynamic Logic Single-Rail Dynamic Logic Dual-Rail Dynamic Logic Clocked CMOS Logic Sequential Logic Designs Sequential Logic Fundamentals Memory Elements Timing Issues in Clocked Systems Pipeline Systems Datapath Subsystem Designs Basic Combinational Components Basic Sequential Components Shifters Addition/Subtraction Multiplication Division Memory Subsystems Introduction Static Random-Access Memory Dynamic Random-Access Memory Read-Only Memory Nonvolatile Memory Other Memory Devices Design Methodologies and Implementation Options Design Methodologies and Implementation Architectures Synthesis Flows Implementation Options of Digital Systems A Case Study | A Simple Start/Stop Timer Interconnect RLC Parasitics Interconnect and Simulation Models Parasitic Effects of Interconnect Transmission-Line Models Advanced Topics Power Distribution and Clock Designs Power Distribution Networks Clock Generation and Distribution Networks Phase-Locked Loops/Delay-Locked Loops Input/Output Modules and ESD Protection Networks General Chip Organizations Output Drivers/Buffers Electrostatic Discharge Protection Networks Testing, Verification, and Testable Designs An Overview of VLSI Testing Fault Models Automatic Test Pattern Generation Testable Circuit Designs System-Level Testing An Introduction to Verilog HDL/SystemVerilog Introduction Behavioral Modeling Hierarchical Structural Modeling Combinational Logic Modules Sequential Logic Modules Synthesis Verification A Start/Stop Timer Index

Proceedings ArticleDOI
05 Sep 2011
TL;DR: The performance gap between embedded and soft multipliers is measured and the design space is explored and the current performance gap is reduced by employing a number of target specific mapping and arithmetic transformation techniques.
Abstract: To bridge the gap between FPGAs and ASICs for arithmetic dominated circuits, one key step is to improve multipliers on FPGAs. This is a key feature that FPGA vendors have tried to improve in recent years by embedding ASIC like multipliers in the DSP blocks. However, due to the limited number of DSP blocks in an FPGA, their fixed location and bit-width limitation, efficient soft logic implementation of multipliers is fundamental. This is the reason that FPGA vendors have enhanced the logic blocks architecture to improve certain arithmetic circuits such as adder tree, which is the basic part of a parallel multiplier. This paper has two main contributions: (1) The performance gap between embedded and soft multipliers is measured and the design space is explored and (2) the current performance gap is reduced by employing a number of target specific mapping and arithmetic transformation techniques. For this purpose, a multiplier generator tool is developed and two conventional multiplication techniques are implemented in this tool. We compare our multipliers with the ones that are generated by Altera core generator tool considering a wide range of bit-widths. Therefore, this paper can be used as a reference for the digital circuit designers to choose the right way of implementing multipliers on FPGAs based on their design constraints.

Journal ArticleDOI
TL;DR: In this paper, a superconducting microwave power divider for RQL logic was proposed, using combination of AC power and SFQ data encoding, with zero static power dissipation.
Abstract: We present design, analysis and test of a superconducting microwave power divider for a new superconducting Reciprocal Quantum Logic (RQL). The RQL logic family, using combination of AC power and SFQ data encoding, allows scalable superconducting digital circuits with zero static power dissipation. The Wilkinson 1:8 power splitter/combiner based on λ/4 resonators has been analyzed for geometric series and maximum flat response. Simulated maximum flat response gives one octave of bandwidth with non-uniformity of the bias current distribution within ±10%. This result is valid with up to 40 ps of electrical length mismatch in the power lines that is well within the requirements for complex circuits. We have experimentally confirmed correct operation of the divider/combiner in a frequency band 0-12 GHz in even mode.

Proceedings ArticleDOI
19 Jul 2011
TL;DR: A new design for T flip flop (T-FF), by using of special feature of QCA circuits capabilities, is proposed, which has additional inputs that can be used better in sequential circuits as memory elements.
Abstract: QCA is a novel technology which provides implementation of digital circuits in nanoscale. QCA circuits work in higher speed, smaller size and less power consumption compared to conventional CMOS circuits. In this paper, a new design for T flip flop (T-FF), by using of special feature of QCA circuits capabilities, is proposed. This T-FF has additional inputs that can be used better in sequential circuits as memory elements. These inputs can reset and preset T-FF and no more cells needed to add them to the designed circuit. Proposed T-FF is simulated using the QCADesigner and simulation results prove its validity.

Patent
25 May 2011
TL;DR: In this paper, a pipelined analog-to-digital converter (ADC) capable of carrying out background digital calibration is presented, which comprises a sampling hold circuit, M calibrated level circuit modules, N level circuit module and a back level analog to digital conversion module which are sequentially connected in series.
Abstract: The invention discloses a pipelined analog-digital converter (ADC) capable of carrying out background digital calibration. The pipelined (ADC) comprises a sampling hold circuit, M calibrated level circuit modules, N level circuit modules and a back level analog-to-digital conversion module which are sequentially connected in series, wherein each calibrated level circuit module is connected with a corresponding digital calibrated level circuit; the quantized value output port of the level circuit module and the quantized value output port of a back level analog-to-digital conversion module are respectively connected with a time delay and dislocation summation module; and the output end of the time delay and dislocation summation module is sequentially and reversely connected in series in the digital calibrated level circuit. The pipelined analog-to-digital converter provided by the invention has the advantages that the thinking is inventive, the analog circuit has a simple structure, a pseudo random number generator and a multi-way selection switch are additionally arranged on the foundation of the existing technical structure, and the working of other analog circuits can not be unaffected in the working process; and simultaneously, the principle of the digital circuit segment is simple and is easy to realize, the error of the pipelined ADC can be reduced obviously, the linearity of the pipelined ADC can be improved, and the dynamic properties of the pipelined ADC can be improved.

Patent
03 Jun 2011
TL;DR: In this article, a self-reconfigurable analog resonant computer employing a fixed electronic circuit schematic which performs computing logic operations (for example OR, AND, NOR, and XOR Boolean logic) without physical rewiring and whose components only include passive circuit elements such as resistors, capacitors, inductors, and memristor devices is presented.
Abstract: An apparatus which provides a self-reconfigurable analog resonant computer employing a fixed electronic circuit schematic which performs computing logic operations (for example OR, AND, NOR, and XOR Boolean logic) without physical re-wiring and whose components only include passive circuit elements such as resistors, capacitors, inductors, and memristor devices The computational logic self-reconfiguration process in the circuit takes place as training input signals, which are input causing the impedance state of the memristor device to change Once the training process is completed, the circuit is probed to determine whether the desired logic operation has been programmed

Proceedings ArticleDOI
19 Dec 2011
TL;DR: This work proposes a new approach to synthesize the reversible universal QCA logic gate (RUG) with the target to reduce the garbage outputs as well as the number of logic gates to realise a design simultaneously ensuring the defect tolerance.
Abstract: Quantum-dot Cellular Automata (QCA) can be a viable technology for CMPs (chip multi-processors) with thousands of processors. The QCA based reversible logic promises energy efficient design of the digital circuits. However, the requirement of excessive logic gates as well as its high defect rate limit the performance of a QCA based design. This work proposes a new approach to synthesize the reversible universal QCA logic gate (RUG) with the target to reduce the garbage outputs as well as the number of logic gates to realise a design simultaneously ensuring the defect tolerance. A concurrent error detection methodology is introduced to support the online testing of a circuit designed around the RUG. The experimental designs establish that the RUG can ensure an energy saving cost effective realization of testable QCA circuits.