Showing papers on "Digital electronics published in 2012"
TL;DR: This paper presents photonic devices with 3 dB/cm waveguide loss fabricated in an existing commercial electronic 45 nm SOI-CMOS foundry process and demonstrates an 8-channel optical microring-resonator filter bank and optical modulators, both controlled by integrated digital circuits.
Abstract: This paper presents photonic devices with 3 dB/cm waveguide loss fabricated in an existing commercial electronic 45 nm SOI-CMOS foundry process. By utilizing existing front-end fabrication processes the photonic devices are monolithically integrated with electronics in the same physical device layer as transistors achieving 4 ps logic stage delay, without degradation in transistor performance. We demonstrate an 8-channel optical microring-resonator filter bank and optical modulators, both controlled by integrated digital circuits. By developing a device design methodology that requires zero process infrastructure changes, a widely available platform for high-performance photonic-electronic integrated circuits is enabled.
235 citations
TL;DR: Using a robust 2:1 multiplexer, efficient level triggered and edge triggered QCA D flip flops and a memory cell with set/reset ability will be introduced and results demonstrate that the proposed desgins have efficient structures in terms of area, delay and complexity.
134 citations
01 Jun 2012
TL;DR: In this work, memristor-based digital logic holds great potential for high-density and energy-efficient computing through its potential use in dense programmable logic circuits.
Abstract: The recent emergence of the memristor has led to a great deal of research into the potential uses of the devices. Specifically, the innate reconfigurability of memristors can be exploited for applications ranging from multilevel memory, programmable logic, and neuromorphic computing, to name a few. In this work, memristors are explored for their potential use in dense programmable logic circuits. While much of the work is focused on Boolean logic, nontraditional styles including threshold logic and neuromorhpic computing are also considered. In addition to an analysis of the circuits themselves, computer-aided design (CAD) flows are presented which have been used to map digital logic functionality to dense complementary metal-oxide-semiconductor (CMOS)-memristive logic arrays. As exemplified through the circuits described here memristor-based digital logic holds great potential for high-density and energy-efficient computing.
120 citations
TL;DR: In this article, the authors present the test results of superconductor-insulator-ferromagnet-superconductor (SIFS) MJJs showing their applicability for superconducting spintronic memory and digital circuits.
112 citations
TL;DR: The RS latch in this TRNG is implemented as a hard-macro to guarantee the quality of randomness by minimizing the signal skew and load imbalance of internal nodes.
Abstract: SUMMARY True random number generators (TRNGs) are important as a basis for computer security. Though there are some TRNGs composed of analog circuit, the use of digital circuits is desired for the application of TRNGs to logic LSIs. Some of the digital TRNGs utilize jitter in freerunning ring oscillators as a source of entropy, which consume large power. Another type of TRNG exploits the metastability of a latch to generate entropy. Although this kind of TRNG has been mostly implemented with fullcustom LSI technology, this study presents an implementation based on common FPGA technology. Our TRNG is comprised of logic gates only, and can be integrated in any kind of logic LSI. The RS latch in our TRNG is implemented as a hard-macro to guarantee the quality of randomness by minimizing the signal skew and load imbalance of internal nodes. To improve the quality and throughput, the output of 64–256 latches are XOR’ed. The derived design was verified on a Xilinx Virtex-4 FPGA (XC4VFX20), and passed NIST statistical test suite without post-processing. Our TRNG with 256 latches occupies 580 slices, while achieving 12.5Mbps through
92 citations
TL;DR: The proposed fault-detection method significantly reduces memory access time when there is no error in the data read and uses the majority logic decoder itself to detect failures, which makes the area overhead minimal and keeps the extra power consumption low.
Abstract: Nowadays, single event upsets (SEUs) altering digital circuits are becoming a bigger concern for memory applications. This paper presents an error-detection method for difference-set cyclic codes with majority logic decoding. Majority logic decodable codes are suitable for memory applications due to their capability to correct a large number of errors. However, they require a large decoding time that impacts memory performance. The proposed fault-detection method significantly reduces memory access time when there is no error in the data read. The technique uses the majority logic decoder itself to detect failures, which makes the area overhead minimal and keeps the extra power consumption low.
89 citations
TL;DR: This work presents a new implementation of digital fluidic logic fully analogous to electronic logic with significant performance advances over the previous implementations, and shows cascade-ability, feedback, programmability, bi-stability, and autonomous control capability.
Abstract: Advances in microfluidics now allow an unprecedented level of parallelization and integration of biochemical reactions. However, one challenge still faced by the field has been the complexity and cost of the control hardware: one external pressure signal has been required for each independently actuated set of valves on chip. Using a simple post-modification to the multilayer soft lithography fabrication process, we present a new implementation of digital fluidic logic fully analogous to electronic logic with significant performance advances over the previous implementations. We demonstrate a novel normally closed static gain valve capable of modulating pressure signals in a fashion analogous to an electronic transistor. We utilize these valves to build complex fluidic logic circuits capable of arbitrary control of flows by processing binary input signals (pressure (1) and atmosphere (0)). We demonstrate logic gates and devices including NOT, NAND and NOR gates, bi-stable flip-flops, gated flip-flops (latches), oscillators, self-driven peristaltic pumps, delay flip-flops, and a 12-bit shift register built using static gain valves. This fluidic logic shows cascade-ability, feedback, programmability, bi-stability, and autonomous control capability. This implementation of fluidic logic yields significantly smaller devices, higher clock rates, simple designs, easy fabrication, and integration into MSL microfluidics.
86 citations
TL;DR: The first experimental demonstration of single flux quantum logic, eSFQ, was reported in this article. But the authors did not report the performance metrics of the eSFLQ circuits.
Abstract: We report the first experimental demonstration of recently proposed energy-efficient single flux quantum logic, eSFQ. This logic can represent the next generation of RSFQ logic eliminating dominant static power dissipation associated with a dc bias current distribution and providing over two orders of magnitude efficiency improvement over conventional RSFQ logic. We further demonstrate that the introduction of passive phase shifters allows the reduction of dynamic power dissipation by about 20%, reaching ~0.8 aJ per bit operation. Two types of demonstration eSFQ circuits, shift registers and demultiplexers (deserializers), were implemented using the standard HYPRES 4.5 kA/cm2 fabrication process. In this paper, we present eSFQ circuit design and demonstrate the viability and performance metrics of eSFQ circuits through simulations and experimental testing.
76 citations
TL;DR: A scalable and reconfigurable optical directed-logic architecture consisting of a regular array of integrated optical switches based on microring resonators that can be reconfigured to perform arbitrary two-input logic functions.
Abstract: We demonstrate a scalable and reconfigurable optical directed-logic architecture consisting of a regular array of integrated optical switches based on microring resonators. The switches are controlled by electrical input logic signals through embedded p-i-n junctions. The circuit can be reconfigured to perform any combinational logic operation by thermally tuning the operation modes of the switches. Here we show experimentally a directed logic circuit based on a 2×2 array of switches. The circuit is reconfigured to perform arbitrary two-input logic functions.
74 citations
01 Dec 2012
TL;DR: In this article, the authors discuss the large-scale CVD growth of single-layer MoS 2 and fabrication of integrated devices and circuits for the first time, such as inverters and NAND gates.
Abstract: 2D nanoelectronics based on single-layer MoS 2 offers great advantages for both conventional and ubiquitous applications. This paper discusses the large-scale CVD growth of single-layer MoS 2 and fabrication of integrated devices and circuits for the first time. Fundamental building blocks of digital electronics, such as inverters and NAND gates, are fabricated to demonstrate its capability for logic applications.
70 citations
TL;DR: Graphene complementary inverters which operate with the same input and output voltage logic levels, thus allowing cascading are demonstrated and signal matching under ambient conditions is obtained.
Abstract: The fundamental building blocks of digital electronics are logic gates which must be capable of cascading such that more complex logic functions can be realized. Here we demonstrate integrated graphene complementary inverters which operate with the same input and output voltage logic levels, thus allowing cascading. We obtain signal matching under ambient conditions with inverters fabricated from wafer-scale graphene grown by chemical vapor deposition (CVD). Monolayer graphene was incorporated in self-aligned field-effect transistors in which the top gate overlaps with the source and drain contacts. This results in full-channel gating and leads to the highest low-frequency voltage gain reported so far in top-gated CVD graphene devices operating in air ambient, Av ∼ −5. Such gain enabled logic inverters with the same voltage swing of 0.56 V at their input and output. Graphene inverters could find their way in realistic applications where high-speed operation is desired but power dissipation is not a concer...
TL;DR: A new style of magnetic logic-mLogic-enabled by a novel four-terminal device is introduced, with SPICE simulation of logic gates demonstrating correct logic operation at supplies below 100 mV.
Abstract: Spintronics is an emerging platform for logic circuit design. Though many approaches have been proposed, and several have met with some success, a number of challenges remain. Here, we introduce a new style of magnetic logic-mLogic-enabled by a novel four-terminal device. An input current pulse to the device switches the magnetic state by spin transfer torque-driven domain wall motion, which programs the resistance state of a magnetic tunnel junction in an electrically-insulated but magnetically-coupled path. Despite the low switching ratios of the devices, limited by the tunnel magnetoresistance ratio, logic circuits independent of CMOS may be configured using current-based signaling. Micromagnetic analysis of device performance and the concepts of mLogic circuit design are introduced, with SPICE simulation of logic gates demonstrating correct logic operation at supplies below 100 mV.
TL;DR: In this article, a modification of the Fredkin gate is proposed and an all-optical circuit of this modified gate is also designed using semiconductor optical amplifier on the Mach-Zehnder interferometer switch.
Abstract: Conventional digital circuits lose energy because the bits of information are destroyed during the operation. Reversible circuits are currently on the top approaches to power minimization with its application in all-optical-based systems. Fredkin gate is a very common reversible logic gate. In this paper, a modification of the Fredkin gate is proposed. All-optical circuit of this modified Fredkin gate (MFG) is also designed using semiconductor optical amplifier on the Mach-Zehnder interferometer switch. A 16-Boolean logical operational circuit is also shown using this MFG. The main advantage of this scheme is that we can design a 15-Boolean logical function using a single MFG unit. Only one operation (nand) required two MFG units. Hence, complexity of the circuit can be reduced. Also, multivalued T-gate circuit using MFG is proposed.
Book•
19 Mar 2012
TL;DR: In this paper, the authors proposed an approach to minimize leakage power in embedded MTCMOS Combinational Circuits using sleep transistors using hybrid heuristics and a 2.5 Gbit/s 1:8 Demultiplexer.
Abstract: 1. Introduction.- References.- 2. Leakage Power: Challenges and Solutions.- 2.1 Introduction.- 2.2 Power Dissipation in CMOS Digital Circuits.- 2.3 Impact of Technology Scaling on Leakage Power.- 2.4 (Vdd-Vth) Design Space.- 2.5 Total Power Management.- 2.6 Leakage Power Control Circuit Techniques.- 2.7 Chapter Summary.- References.- 3. Embedded Mtcmos Combinational Circuits.- 3.1 Introduction.- 3.2 Basic Concept.- 3.3 The Power Minimization Problem.- 3.4 Algorithms.- 3.5 Choosing the High-Vth Value.- 3.6 Chapter Summary.- References.- 4. Mtcmos Combinational Circuits Using Sleep Transistors.- 4.1 Introduction.- 4.2 MTCMOS Design: Overview.- 4.3 Variable Breakpoint Switch Level Simulator [1].- 4.4 Hierarchical Sizing Based on Mutually Exclusive Discharge Patterns.- 4.5 Designing High-Vth Sleep Transistors, the Average Current Method [6].- 4.6 Drawbacks of Techniques.- 4.7 Distributed Sleep Transistors [9] [10].- 4.8 Clustering Techniques.- 4.9 Hybrid Heuristic Techniques.- 4.10 Virtual Ground Bounce.- 4.11 Results: Taking ground bounce into account.- 4.12 Power Management of Sleep Transistors.- 4.13 Chapter Summary.- References.- 5. Mtcmos Sequential Circuits.- 5.1 Introduction.- 5.2 MTCMOS Latch Circuit.- 5.3 MTCMOS Balloon Circuit.- 5.4 Intermittent Power Supply Scheme.- 5.5 Auto-Backgate-Controlled MTCMOS.- 5.6 Virtual Rails Clamp (VRC) Circuit.- 5.7 Leakage Sneak Paths in MTCMOS Sequential Circuits.- 5.8 Interfacing MTCMOS and CMOS blocks.- 5.9 Impact of the High-Vth and Low-Vth values on MTCMOS Sequential Circuit Design.- 5.10 Leakage Feedback Gates.- 5.11 Chapter Summary.- References.- 6. Mtcmos Dynamic Circuits.- 6.1 Introduction.- 6.2 Clock-Delayed Domino Logic: Overview.- 6.3 HS-Domino Logic.- 6.4 MTCMOS CD-Domino Logic: Analysis and Overview.- 6.5 MTCMOS HS-Domino (MHS-Domino) Logic.- 6.6 Domino Dual Cascode Voltage Switch Logic (DDCVSL).- 6.7 Chapter Summary.- References.- 7. Mtcmos Current-Steering Circuits.- 7.1 MOS Current Mode Logic: Overview.- 7.2 Introduction.- 7.3 Minimum Supply Voltage: First Constraint.- 7.4 Saturation Assurance: Second Constraint and the Proposed MTCMOS Design.- 7.5 A 2.5 Gbit/s 1:8 Demultiplexer in MTCMOS MCML.- 7.6 Impact of Using MTCMOS Technology Over MCML Parameters.- 7.7 Chapter Summary.- References.
TL;DR: The simulation results reveal better delay and power performance for the proposed modified GDI full adders when compared with the existing GDI technique, CMOS and pass transistor logic at 0.250 μm CMOS technologies.
05 Nov 2012
TL;DR: This simulation study shows that most of the defects in FinFET logic circuits can be covered with existing fault models, but they vary under different cases and test strategies may need to be augmented to target them.
Abstract: FinFET transistor has much better short-channel characteristics than traditional planar CMOS transistor and will be widely used in next generation technology. Due to its significant structural difference from conventional planar devices, it is essential to revisit whether existing fault models are applicable to detect faults in FinFET logic gates. In this paper, we study some unique defects in FinFET logic circuits and simulate their faulty behavior. Our simulation study shows that most of the defects can be covered with existing fault models, but they vary under different cases and test strategies may need to be augmented to target them.
01 Jan 2012
TL;DR: Field Programmable Gate Arrays have seen a rapid growth and have become a popular implementation media for digital circuits and have a dramatic effect on the quality of final device’s area, speed, and power consumption.
Abstract: Field Programmable Gate Arrays (FPGAs) were first introduced almost two and a half decades ago. Since then they have seen a rapid growth and have become a popular implementation media for digital circuits. The advancement in process technology has greatly enhanced the logic capacity of FPGAs and has in turn made them a viable implementation alternative for larger and complex designs. Further, programmable nature of their logic and routing resources has a dramatic effect on the quality of final device’s area, speed, and power consumption.
TL;DR: Low-power Majority-function-based 1-bit full addersthat use MOS capacitors (MOSCAP) in its structure is presented that helps in reducing power consumption, propagation delay, and area of digital circuits while maintaining low complexity of logic design.
Abstract: This paper presents a comparative study of high-speed and low-voltage full adder circuits. Our approach is based on hybrid design full adder circuits combined in a single unit. A high performance adder cell using an XOR-XNOR (3T) design style is discussed. This paper also discusses a high-speed conventional full adder design combined with MOSCAP Majority function circuit in one unit to implement a hybrid full adder circuit. Moreover, it presents low-power Majority-function-based 1-bit full addersthat use MOS capacitors (MOSCAP) in its structure. This technique helps in reducing power consumption, propagation delay, and area of digital circuits while maintaining low complexity of logic design. Simulation results illustrate the superiority of the designed adder circuits over the conventional CMOS, TG, and hybrid adder circuits in terms of power, delay, power delay product (PDP), and energy delay product (EDP). Postlayout simulation results illustrate the superiority of the newly designed majority adder circuits against the reported conventional adder circuits. The design is implemented on UMC0.18 µm process models in Cadence Virtuoso Schematic Composer at 1.8 V single-ended supply voltage, and simulations are carried out on Spectre S.
TL;DR: A new design method is proposed that exploits in original ways the properties of auxiliary propagate and generates signals to reduce the number of majority gates required to implement adders in QCA and/or the addition time.
Abstract: The quantum-dot cellular automata (QCA) approach is an attractive emerging technology suitable for the development of ultradense low-power high-performance digital circuits. Even though several solutions have been proposed recently for binary addition circuits, the design of efficient adders in QCA still poses several challenges since, most often, designers tend to implement strategies and methodologies close to those consolidated for the CMOS logic design. In this paper, we propose a new design method that exploits in original ways the properties of auxiliary propagate and generates signals to reduce the number of majority gates required to implement adders in QCA and/or the addition time. Three new formulations of basic logic equations frequently used in the designs of fast binary adders are proposed. To evaluate the potential advantage of the new strategy, two examples of application of the aforementioned method are discussed in this paper.
TL;DR: This paper demonstrates that NML circuits can be effectively fabricated not only using electron beam lithography, but also using high-end optical lithography without loosing performance, and demonstrates the robustness of the MV considering process variations and extracting useful guidelines for its technological implementation.
Abstract: The recently proposed Nanomagnet-based logic (NML) represents an innovative way to assemble electronic logic circuits. The low power consumption, combined with the possibility of maintaining the information stored without power supply, allows us to design low power digital circuits far beyond the limitations of CMOS technology. This paper is focused on the key logic block of NML, the majority voter (MV). It is thoroughly analyzed through detailed micromagnetic simulations, changing the geometrical parameters, and detecting logic behavior, timing performance, and energy dissipation. Our analysis enables us to derive important results, substantially enhancing the practical knowledge of NML. First, we demonstrate that NML circuits can be effectively fabricated not only using electron beam lithography, but also using high-end optical lithography without loosing performance. This is a promising opportunity for the future of this technology. Second, we demonstrate the robustness of the MV considering process variations and extracting useful guidelines for its technological implementation. Third, we show how, and how much, the alteration of magnets sizes and distances affect timing and energy consumption. Finally, fourth, we outline the problematic fabrication of the gate with real clock wires, and propose a modification that enables the fabrication of working gates, remarkably enhancing the possibilities of this technology.
03 Apr 2012
TL;DR: This work presents a digital WiFi transmitter (TX) implemented in a 32nm digital CMOS process to address issues of outphasing PA design, and achieves state-of-the-art performance already in 32nm and is moreover expected to improve with scaling and port easily over successive process nodes.
Abstract: Integration of radios in SoCs along with digital baseband and application processors is desirable for cost and form-factor reasons. Digital processors are typically implemented in the latest CMOS process to take advantage of the increased density and performance afforded by CMOS scaling. Integration of traditional RF circuits, however, requires accurate RF and passive models that typically lag behind digital transistor models by several quarters. This makes RF integration the limiting factor for time-to-market for the whole SoC, or results in sub-optimal multiple-chip solutions. Furthermore, traditional RF circuits do not benefit from scaling as digital circuits do, e.g. due to extensive use of inductors, the ever-lowering supply voltage, etc. This work presents a digital WiFi transmitter (TX) implemented in a 32nm digital CMOS process to address these issues. An outphasing architecture allows implementation of both amplitude and phase modulation using scaling-friendly, delay-based, switching phase modulators. The integrated PA was already shown to be possible to design with no RF models [1]; known issues of outphasing PA design (e.g. output impedance modulation, linearity, efficiency) are also addressed in [1]. The phase modulator uses an open-loop architecture to accommodate OFDM bandwidths up to 40MHz. The TX achieves state-of-the-art performance already in 32nm and is moreover expected to: (1) improve with scaling and (2) port easily over successive process nodes.
01 Oct 2012
TL;DR: The basic theory of QCA cell and some fundamental gates ofQCA scheme are presented and several design of sequential circuits such as gated D latch, RS latch, JK flip-flop, T flip- flop, D flip-Flop, 2-bit counter, 4-bitcounter, and 4- bit shift register are presented in QCA architecture.
Abstract: As the size of CMOS transistors keep shrinking, it will eventually hit its limitation. Hence, an alternative device has to be discovered to continually improve the development of electronics devices. Quantum-dot cellular automata (QCA), is a potential device that can be used to implement digital circuits. In this paper, we present the basic theory of QCA cell and some fundamental gates of QCA scheme. The fundamental gates, such as the QCA inverter and QCA majority gate are then used to build more complex logic circuits. Several design of sequential circuits such as gated D latch, RS latch, JK flip-flop, T flip-flop, D flip-flop, 2-bit counter, 4-bit counter, and 4-bit shift register are presented in QCA architecture. These designs are captured and simulated using a design software called QCADesigner.
30 Apr 2012
TL;DR: Several simulations conducted using different voltage supplies, load capacitors and temperature variation demonstrate the superiority of the XOR (3T) based full adder designs in term of delay, power and power delay product (PDP) compared to the other fullAdder circuits.
Abstract: This paper presents comparative study of high-speed, low-power and low voltage full adder circuits. Our approach is based on XOR-XNOR design full adder circuits in a single unit. A low power and high performance 9T full adder cell using a design style called “XOR (3T)” is discussed. The designed circuit commands a high degree of regularity and symmetric higher density than the conventional CMOS design style as well as it lowers power consumption by using XOR (3T) logic circuits. Gate Diffusion Input (GDI) technique of low-power digital combinatorial circuit design is also described. This technique helps in reducing the power consumption and the area of digital circuits while maintaining low complexity of logic design. This paper analyses, evaluates and compares the performance of various adder circuits. Several simulations conducted using different voltage supplies, load capacitors and temperature variation demonstrate the superiority of the XOR (3T) based full adder designs in term of delay, power and power delay product (PDP) compared to the other full adder circuits. Simulation results illustrate the superiority of the designed adder circuits against the conventional CMOS, TG and Hybrid full adder circuits in terms of power, delay and power delay product (PDP).
TL;DR: This brief proposes a set of efficient NBTI-aware circuit design solutions that aim at improving the lifetime stability of power-gated circuits by means of oversizing, body biasing, and stress-probability reduction while minimizing the design overheads.
Abstract: While negative bias temperature instability (NBTI) effects on logic gates are of major concern for the reliability of digital circuits, they become even more critical when considering the components for which even minimal parametric variations impact the lifetime of the overall circuit. pMOS header transistors used in power-gated architectures are one relevant example of such components. For these types of devices, an NBTI-induced current capability degradation translates into a larger -drop effect on the virtual- rail, which unconditionally affects the performance and, thus, the reliability of all power-gated cells. In this brief, we address the problem of designing NBTI-tolerant power-gating architectures. We propose a set of efficient NBTI-aware circuit design solutions, including both static and dynamic strategies, that aim at improving the lifetime stability of power-gated circuits by means of oversizing, body biasing, and stress-probability reduction while minimizing the design overheads. Experimental results prove the effectiveness of such techniques when applied to a suite of benchmarks mapped onto a 45-nm industrial CMOS technology library. In particular, we prove that it is possible to achieve more than ten times of lifetime extension with respect to a traditional power-gating approach.
TL;DR: An ultra-compact model for nanometer CMOS transistors, suitable for the analysis of digital circuits, is proposed and the model is shown to allow an accurate and quick estimation of parameters such as delay or dc transfer curves.
Abstract: In this paper, an ultra-compact model for nanometer CMOS transistors, suitable for the analysis of digital circuits, is proposed. Starting from modified and more accurate versions of classical compact models, an extremely simple one (nine parameters and piecewise linear versus relationships in both triode and saturation) is extracted. All the main physical effects that are predominant in nanometer technologies are included and the model is shown to allow an accurate and quick estimation of parameters such as delay or dc transfer curves. Simulation results are extracted in a 65-nm CMOS technology.
TL;DR: In this article, the design, fabrication, and electrical characteristics of inverter, NAND, and NOR logic circuits using 6H-silicon carbide (SiC) depletion-mode junction field effect transistors are reported.
Abstract: This letter reports the design, fabrication, and electrical characteristics of inverter, NAND, and NOR logic circuits using 6H-silicon carbide (SiC) depletion-mode junction field-effect transistors All circuits function with high performance at temperatures from 25 °C to 550 °C The core inverter has an outstanding dc characteristic transfer function with a steep slope, including a gain of >; -20 up to 500 °C, and a logic threshold that is well centered in the logic swing NOR and NAND gates were likewise tested in this temperature range, and dynamic characteristics are presented This SiC technology provides a platform for applications demanding reliable digital circuits at temperatures higher than 300 °C, well beyond the capability of silicon technology
TL;DR: In this article, an analog circuit model is constructed from the developed transfer function via a network synthesis method, and a digital model is presented by transforming the developed transferred function into a digital domain transfer function using bilinear transformation.
Abstract: Optical current transformers/transducers (OCTs) produce digital and analog signals. In recent years, they have become more available, playing an increasingly important role in electric power grid upgrades. This requires developing accurate models for relay testing and relay performance evaluations to ensure that the system equipment is safe. This study presents several models developed for OCT: analog, digital, and complete models. It applies previously studied and presented frequency-response characteristics to develop a transfer function using a complex curve-fitting method. An analog circuit model is constructed from the developed transfer function via a network synthesis method. A digital model is presented by transforming the developed transfer function into a digital domain transfer function using bilinear transformation. The digital model implementation is performed by the direct form I block diagram. The optics model and electronics model of the device are developed separately and are then combined to present a complete model. The Jones calculus method is used for optical modeling, and a developed transfer function is used for electronics modeling. All of the developed models are verified through the frequency-response results and tested with PSpice and Matlab Simulink programs. The results show that the developed models can be used as legitimate OCT models.
18 Oct 2012
TL;DR: This paper presents a new stateful logic operation available for rectifying memristors which corresponds to the logical operation known as the converse nonimplication, and shows that it solves the fan-out problem.
Abstract: In its elementary form, memristive implication logic suffers from multiple disadvantages such as the lengths of the computational sequences required to synthesize a Boolean function, the lack of fan-out, and the requirement of complex control signals. In this paper we present a new stateful logic operation available for rectifying memristors which corresponds to the logical operation known as the converse nonimplication, and show that it solves the fan-out problem. Moreover, we show how parallel stateful logic can be performed within a CMOL memory architecture, and how it can be used to shorten the computational sequences. We also discuss applications where stateful logic could be advantageous when compared to more conventional solutions.
14 May 2012
TL;DR: The experiments show that incorporating negative control lines in the circuits to be synthesized leads to smaller circuits with respect to the number of gates and in some cases even the run-time of the synthesis can be improved.
Abstract: The development of synthesis approaches for reversible circuits is an active research area. Besides heuristic methods, also exact synthesis received significant attention. Here, circuits realizing the desired functions e.g. with a minimal number of gates are determined. However, so far exact synthesis considering Toffoli gate circuits with positive control lines only has been considered. In this paper, we are extending the scope of exact synthesis by additionally considering negative control lines in the circuits to be synthesized. For this purpose, we propose and evaluate a SAT-based synthesis method. Our experiments show that incorporating negative control lines leads to smaller circuits with respect to the number of gates. Furthermore, in some cases even the run-time of the synthesis can be improved.
TL;DR: Different optical logic gates are demonstrated using a single Mach-Zehnder interferometer with controlled phase modulators in each arm, and the proposed configuration presents significant low complexity and high scalability.
Abstract: In this paper, we demonstrate different optical logic gates using a single Mach–Zehnder interferometer with controlled phase modulators in each arm. The operational conditions to obtain 16 optical logic circuits, using the same design, are investigated and are a result of a constructive or destructive interference process. The proposed configuration presents significant low complexity and high scalability, and its feasibility is evaluated through numerical simulations.