Showing papers on "Digital electronics published in 2014"

Neurogrid: A Mixed-Analog-Digital Multichip System for Large-Scale Neural Simulations

Abstract: In this paper, we describe the design of Neurogrid, a neuromorphic system for simulating large-scale neural models in real time. Neuromorphic systems realize the function of biological neural systems by emulating their structure. Designers of such systems face three major design choices: 1) whether to emulate the four neural elements-axonal arbor, synapse, dendritic tree, and soma-with dedicated or shared electronic circuits; 2) whether to implement these electronic circuits in an analog or digital manner; and 3) whether to interconnect arrays of these silicon neurons with a mesh or a tree network. The choices we made were: 1) we emulated all neural elements except the soma with shared electronic circuits; this choice maximized the number of synaptic connections; 2) we realized all electronic circuits except those for axonal arbors in an analog manner; this choice maximized energy efficiency; and 3) we interconnected neural arrays in a tree network; this choice maximized throughput. These three choices made it possible to simulate a million neurons with billions of synaptic connections in real time-for the first time-using 16 Neurocores integrated on a board that consumes three watts.

Memristor-Based Material Implication (IMPLY) Logic: Design Principles and Methodologies

Abstract: Memristors are novel devices, useful as memory at all hierarchies. These devices can also behave as logic circuits. In this paper, the IMPLY logic gate, a memristor-based logic circuit, is described. In this memristive logic family, each memristor is used as an input, output, computational logic element, and latch in different stages of the computing process. The logical state is determined by the resistance of the memristor. This logic family can be integrated within a memristor-based crossbar, commonly used for memory. In this paper, a methodology for designing this logic family is proposed. The design methodology is based on a general design flow, suitable for all deterministic memristive logic families, and includes some additional design constraints to support the IMPLY logic family. An IMPLY 8-bit full adder based on this design methodology is presented as a case study.

Gate-length biasing for digital circuit optimization

Abstract: Methods and apparatus for a gate-length biasing methodology for optimizing integrated digital circuits are described. The gate-length biasing methodology replaces a nominal gate-length of a transistor with a biased gate-length, where the biased gate-length includes a bias length that is small compared to the nominal gate-length. In an exemplary embodiment, the bias length is less than 10% of the nominal gate-length.

MoS2 transistors operating at gigahertz frequencies.

Abstract: The presence of a direct band gap 1−4 and an ultrathin form factor 5 has caused a considerable interest in two-dimensional (2D) semiconductors from the transition metal dichalcogenides (TMD) family with molybdenum disulfide (MoS2) being the most studied representative of this family of materials. While diverse electronic elements, 6,7 logic circuits, 8,9 and optoelectronic devices 12,13 have been demonstrated using ultrathin MoS2, very little is known about their performance at high frequencies where commercial devices are expected to function. Here, we report on top-gated MoS2 transistors operating in the gigahertz range of frequencies. Our devices show cutoff frequencies reaching 6 GHz. The presence of a band gap also gives rise to current saturation, 10 allowing power and voltage gain, all in the gigahertz range. This shows that MoS2 could be an interesting material for realizing high-speed amplifiers and logic circuits with device scaling expected to result in further improvement of performance. Our work represents the first step in the realization of high-frequency analog and digital circuits based on 2D semiconductors.

Reverse Engineering Digital Circuits Using Structural and Functional Analyses

Abstract: Integrated circuits (ICs) are now designed and fabricated in a globalized multivendor environment making them vulnerable to malicious design changes, the insertion of hardware Trojans/malware, and intellectual property (IP) theft. Algorithmic reverse engineering of digital circuits can mitigate these concerns by enabling analysts to detect malicious hardware, verify the integrity of ICs, and detect IP violations. In this paper, we present a set of algorithms for the reverse engineering of digital circuits starting from an unstructured netlist and resulting in a high-level netlist with components such as register files, counters, adders, and subtractors. Our techniques require no manual intervention and experiments show that they determine the functionality of ${>}{45\%}$ and up to 93% of the gates in each of the test circuits that we examine. We also demonstrate that our algorithms are scalable to real designs by experimenting with a very large, highly-optimized system-on-chip (SOC) design with over 375000 combinational elements. Our inference algorithms cover 68% of the gates in this SOC. We also demonstrate that our algorithms are effective in aiding a human analyst to detect hardware Trojans in an unstructured netlist.

Design and Evaluation of Multiple Valued Logic Gates Using Pseudo N-Type Carbon Nanotube FETs

Abstract: Multiple valued logic (MVL) circuits are particularly attractive for nanoscale implementation as advantages in information density and operating speed can be harvested using emerging technologies. In this paper, a new family of MVL gates is proposed for implementation using carbon nanotube field-effect transistors (CNTFETs). The proposed designs use pseudo N-type CNTFETs and no resistor is utilized for their operation. This approach exploits threshold voltage control of the P-type and N-type transistors, while ensuring correct MVL operation for both ternary and quaternary logic gates. This paper provides a detailed assessment of several figures of merit, such as static power consumption, switching power consumption, propagation delay and the power-delay product (PDP). Compared with resistor-loaded designs, the proposed pseudo-NCNTFET MVL gates show advantages in circuit area, power consumption and energy efficiency, while still incurring a comparable propagation delay. Compared to a complementary logic family, the pseudo-NCNTFET MVL logic family requires a smaller circuit area with a similar propagation delay on average, albeit with a larger PDP and static power consumption. A design methodology and a discussion of issues related to leakage and yield are also provided for the proposed MVL logic family.

Elementary Aspects for Circuit Implementation of Reconfigurable Nanowire Transistors

Abstract: A feasibility and performance study of electrically reconfigurable nanowire transistors with selectable pFET and nFET operations is presented. The challenges toward circuit implementation are evaluated based on transient simulations of logic circuits. A novel physical structure capable of computing a NAND as well as NOR function is introduced. The new approach provides a flexible platform to develop and test fine-grain reconfigurable circuits and systems.

An Event-Based Neural Network Architecture With an Asynchronous Programmable Synaptic Memory

Abstract: We present a hybrid analog/digital very large scale integration (VLSI) implementation of a spiking neural network with programmable synaptic weights. The synaptic weight values are stored in an asynchronous Static Random Access Memory (SRAM) module, which is interfaced to a fast current-mode event-driven DAC for producing synaptic currents with the appropriate amplitude values. These currents are further integrated by current-mode integrator synapses to produce biophysically realistic temporal dynamics. The synapse output currents are then integrated by compact and efficient integrate and fire silicon neuron circuits with spike-frequency adaptation and adjustable refractory period and spike-reset voltage settings. The fabricated chip comprises a total of 32 × 32 SRAM cells, 4 × 32 synapse circuits and 32 × 1 silicon neurons. It acts as a transceiver, receiving asynchronous events in input, performing neural computation with hybrid analog/digital circuits on the input spikes, and eventually producing digital asynchronous events in output. Input, output, and synaptic weight values are transmitted to/from the chip using a common communication protocol based on the Address Event Representation (AER). Using this representation it is possible to interface the device to a workstation or a micro-controller and explore the effect of different types of Spike-Timing Dependent Plasticity (STDP) learning algorithms for updating the synaptic weights values in the SRAM module. We present experimental results demonstrating the correct operation of all the circuits present on the chip.

Synthesis and Optimization of FPGA-Based Systems

Abstract: Part I Design of digital circuits and systems on the basis of FPGA.- Part II Methods for optimization of finite state machines for FPGA-based circuits and systems.

Race logic: a hardware acceleration for dynamic programming algorithms

Abstract: We propose a novel computing approach, dubbed "Race Logic", in which information, instead of being represented as logic levels, as is done in conventional logic, is represented as a timing delay. Under this new information representation, computations can be performed by observing the relative propagation times of signals injected into the circuit (i.e. the outcome of races). Race Logic is especially suited for solving problems related to the

Synthetic analog and digital circuits for cellular computation and memory

Abstract: Biological computation is a major area of focus in synthetic biology because it has the potential to enable a wide range of applications. Synthetic biologists have applied engineering concepts to biological systems in order to construct progressively more complex gene circuits capable of processing information in living cells. Here, we review the current state of computational genetic circuits and describe artificial gene circuits that perform digital and analog computation. We then discuss recent progress in designing gene networks that exhibit memory, and how memory and computation have been integrated to yield more complex systems that can both process and record information. Finally, we suggest new directions for engineering biological circuits capable of computation.

Majority logic gate for 3D magnetic computing.

Abstract: For decades now, microelectronic circuits have been exclusively built from transistors. An alternative way is to use nano-scaled magnets for the realization of digital circuits. This technology, known as nanomagnetic logic (NML), may offer significant improvements in terms of power consumption and integration densities. Further advantages of NML are: non-volatility, radiation hardness, and operation at room temperature. Recent research focuses on the three-dimensional (3D) integration of nanomagnets. Here we show, for the first time, a 3D programmable magnetic logic gate. Its computing operation is based on physically field-interacting nanometer-scaled magnets arranged in a 3D manner. The magnets possess a bistable magnetization state representing the Boolean logic states '0' and '1.' Magneto-optical and magnetic force microscopy measurements prove the correct operation of the gate over many computing cycles. Furthermore, micromagnetic simulations confirm the correct functionality of the gate even for a size in the nanometer-domain. The presented device demonstrates the potential of NML for three-dimensional digital computing, enabling the highest integration densities.

A 32 nm Embedded, Fully-Digital, Phase-Locked Low Dropout Regulator for Fine Grained Power Management in Digital Circuits

Abstract: The need for fine-grained power management in digital ICs has led to the design and implementation of compact, scalable low-drop out regulators (LDOs) embedded deep within logic blocks. While analog LDOs have traditionally been used in digital ICs, the need for digitally implementable LDOs embedded in digital functional units for ultrafine grained power management is paramount. This paper presents a fully-digital, phase locked LDO implemented in 32 nm CMOS. The control model of the proposed design has been provided and limits of stability have been shown. Measurement results with a resistive load as well as a digital load exhibit peak current efficiency of 98%.

Boolean Logic Operations and Computing Circuits Based on Memristors

Abstract: This brief contributes to the design of computational and reconfigurable structures that exploit unique threshold-dependent switching response of single memristors and their compositions. A new logic circuit design paradigm, which assumes parallel processing of input signals, is proposed, along with a methodology for the construction of robust programmable composite memristive switches of variable precision. This methodology is applied to the design of memristive computing circuits. A SPICE simulation-based validation of the proposed circuits and systems is provided.

Static and Clocked Spintronic Circuit Design and Simulation With Performance Analysis Relative to CMOS

Abstract: Spin-based devices, in which information is carried via electron spin rather than electron charge, are potential candidates to complement CMOS technology due to the promise of non-volatility and compact implementation of logic gates. One class of such devices is all-spin logic (ASL) which is based on switching ferromagnets by spin transfer torque and conduction of spin-polarized current. Using previously developed physics-based circuit models for ASL, we develop a complete logic family for static ASL comprising of majority logic gates. We compare its performance metrics by means of circuit simulations using our Verilog-A compact models. We also show the novel implementations of sequencing elements (e.g., latch and D flip-flop) to enable clocked ASL. We also refine the models for ferromagnets to include spin relaxation inside ferromagnetic metals (FMs).

An LDPC Decoder With Time-Domain Analog and Digital Mixed-Signal Processing

Abstract: Time-domain analog and digital mixed-signal processing (TD-AMS) is presented. Analog computation is more energy- and area-efficient at the cost of its limited accuracy, whereas digital computation is more versatile and derives greater benefits from technology scaling. Besides, design automation tools for digital circuits are much more sophisticated than those for analog circuits. TD-AMS exploits both advantages, and is a solution better suited to implementing a system on chip including functions for which high computational accuracy is not required, such as error correction, image processing, and machine learning. As an example, a low-density parity-check (LDPC) code decoder with the technique is implemented in 65 nm CMOS and achieves the best reported efficiencies of 10.4 pJ/bit and 6.1 Gbps/mm2.

A Compact Transregional Model for Digital CMOS Circuits Operating Near Threshold

Abstract: Power dissipation is currently one of the most important design constraints in digital systems. In order to reduce power and energy demands in the foremost technology, namely CMOS, it is necessary to reduce the supply voltage to near the device threshold voltage. Existing analytical models for MOS devices are either too complex, thus obscuring the basic physical relations between voltages and currents, or they are inaccurate and discontinuous around the region of interest, i.e., near threshold. This paper presents a simple transregional compact model for analyzing digital circuits around the threshold voltage. The model is continuous, physically derived (by way of a simplified inversion-charge approximation), and accurate over a wide operational range: from a few times the thermal voltage to approximately twice the threshold voltage in modern technologies.

BDD based synthesis of Boolean functions using memristors

Abstract: Very recently a new passive circuit element called memristor has been extensively investigated by researchers, which can be used for a variety of applications. This two-terminal device having few nanometer dimensions has been experimentally shown to possess both memory and resistor properties. This has also received great attention due to the fact that these devices can very easily be integrated on CMOS subsystems. Most of the logic design works in this context are based on material implication operation which can be very efficiently implemented using memristors. In this paper we propose an efficient realization of 2-to-1 multiplexer using memristors, and hence present a synthesis methodology that represents a given Boolean function as a Reduced Ordered Binary Decision Diagram (ROBDD) and then maps the same to memristor implementation.

A mixed-signal implementation of a polychronous spiking neural network with delay adaptation.

Abstract: We present a mixed-signal implementation of a re-configurable polychronous spiking neural network capable of storing and recalling spatio-temporal patterns. The proposed neural network contains one neuron array and one axon array. Spike Timing Dependent Delay Plasticity is used to fine-tune delays and add dynamics to the network. In our mixed-signal implementation, the neurons and axons have been implemented as both analog and digital circuits. The system thus consists of one FPGA, containing the digital neuron array and the digital axon array, and one analog IC containing the analog neuron array and the analog axon array. The system can be easily configured to use different combinations of each. We present and discuss the experimental results of all combinations of the analog and digital axon arrays and the analog and digital neuron arrays. The test results show that the proposed neural network is capable of successfully recalling more than 85% of stored patterns using both analog and digital circuits.

Impact of technology scaling on the combinational logic soft error rate

Abstract: Experimental results from alpha particle irradiation of 40-nm, 28-nm and 20-nm bulk technology circuits operating in the GHz range suggest that the combinational logic soft error rate (SER) per logic gate decreases with scaling. This rate of decrease for the logic SER with scaling, however, is not as high as that of the latch SER. As a result, the proportion of combinational logic soft errors at the chip level is shown to increase. Results suggest that alpha-particle logic SER of average sized circuits is about 20% of the latch SER at 20-nm node while it is only 10% at 40-nm at 500 MHz. Moreover, the frequency at which combinational logic SER exceeds latch SER decreases with scaling. Factors that influence logic soft error scaling trends, such as sensitive area, transient pulse-widths and latch characteristics, are estimated through simulations and soft-error rate predictions for future technology nodes are made.

Positive-Feedback Level Shifter Logic for Large-Area Electronics

Abstract: Positive-feedback Level Shifter (PLS) logic is proposed in this paper for the design of unipolar digital circuits manufactured at low temperature on foil using organic or metal-oxide semiconductors. Positive feedback and a suitable control voltage provide high gain and a symmetrical input-output characteristic even in presence of large TFT variations, enabling robust digital design. The measured gain improves from 13 dB in traditional Zero-Vgs inverters to 76 dB in PLS inverters; the average noise margin increases from 2.58 V (Zero-Vgs) to 6.82 V (PLS) at 20 V supply. Assuming that a positive noise margin for each gate is the only requirement to obtain a fully functional digital circuit, the maximum number of logic gates compatible with a 90% yield improves from 200 Zero-Vgs inverters to above 24 million PLS inverters. A 240-stage PLS shift-register exploiting 13,440 organic TFTs is indeed successfully measured. This is to the authors' knowledge the organic circuit with the highest transistor count ever demonstrated. The control voltage, always within the supply rails, enables automatic correction of the process variations using linear control circuits. The proposed approach will enable a strong increase in the complexity of large-area electronics on foil, with great benefit to applications like flexible displays and large-area sensing surfaces.

Template-based circuit understanding

Abstract: When verifying or reverse-engineering digital circuits, one often wants to identify and understand small components in a larger system. A possible approach is to show that the sub-circuit under investigation is functionally equivalent to a reference implementation. In many cases, this task is difficult as one may not have full information about the mapping between input and output of the two circuits, or because the equivalence depends on settings of control inputs. We propose a template-based approach that automates this process. It extracts a functional description for a low-level combinational circuit by showing it to be equivalent to a reference implementation, while synthesizing an appropriate mapping of input and output signals and setting of control signals. The method relies on solving an exists/forall problem using an SMT solver, and on a pruning technique based on signature computation.

Logic synthesis and a generalized notation for memristor-realized material implication gates

Abstract: The paper presents new logic synthesis methods for single-output incomplete multi-level binary circuits using Memristor-based material implication gates. The first method follows Lehtonen's assumption of using only two working memristors. The algorithm minimizes the number of implication (IMPLY) gates, which corresponds to minimizing the number of pulses or the delay time. This greedy search method uses essential and secondary essential primes, does not require solving the covering problem, is fast, and produces high quality results. We compare it to other synthesis methods, such as the modified SOP and Exclusive-Or Sum of Products (ESOP) with minimum number of working memristors. We analyze the problem of reduction in IMPLY gate count by adding more working memristors and introduce Imply Sequence Diagrams, a new notation, similar to one used in reversible logic.

A novel method based solely on field programmable gate array (FPGA) units enabling measurement of time and charge of analog signals in positron emission tomography (PET)

Abstract: This article presents an application of a novel technique for precise measurements of time and charge based solely on a field programmable gate array (FPGA) device for positron emission tomography (PET). The described approach simplifies electronic circuits, reduces the power consumption, lowers costs, merges front-end electronics with digital electronics, and also makes more compact final design. Furthermore, it allows to measure time when analog signals cross a reference voltage at dif- ferent threshold levels with a very high precision of ~15 ps (rms) and thus enables sampling of signals in a voltage domain.

Design of Efficient Binary Comparators in Quantum-Dot Cellular Automata

Abstract: Quantum-dot cellular automata (QCA) are an attractive emerging technology suitable for the development of ultra-dense low-power high-performance digital circuits. Efficient solutions have recently been proposed for several arithmetic circuits, such as adders, multipliers, and comparators. Nevertheless, since the design of digital circuits in QCA still poses several challenges, novel implementation strategies and methodologies are highly desirable. This paper proposes a new design approach oriented to the implementation of binary comparators in QCA. New formulations of basic logic equations required to perform the comparison function are proposed. The new strategy has been exploited in the design of two different comparator architectures and for several operands word lengths. With respect to existing counterparts, the comparators proposed here exhibit significantly higher speed and reduced overall area.