Showing papers on "Digital electronics published in 2017"

A Scalable Multicore Architecture With Heterogeneous Memory Structures for Dynamic Neuromorphic Asynchronous Processors (DYNAPs)

Abstract: Neuromorphic computing systems comprise networks of neurons that use asynchronous events for both computation and communication. This type of representation offers several advantages in terms of bandwidth and power consumption in neuromorphic electronic systems. However, managing the traffic of asynchronous events in large scale systems is a daunting task, both in terms of circuit complexity and memory requirements. Here, we present a novel routing methodology that employs both hierarchical and mesh routing strategies and combines heterogeneous memory structures for minimizing both memory requirements and latency, while maximizing programming flexibility to support a wide range of event-based neural network architectures, through parameter configuration. We validated the proposed scheme in a prototype multicore neuromorphic processor chip that employs hybrid analog/digital circuits for emulating synapse and neuron dynamics together with asynchronous digital circuits for managing the address-event traffic. We present a theoretical analysis of the proposed connectivity scheme, describe the methods and circuits used to implement such scheme, and characterize the prototype chip. Finally, we demonstrate the use of the neuromorphic processor with a convolutional neural network for the real-time classification of visual symbols being flashed to a dynamic vision sensor (DVS) at high speed.

Stochastic p -Bits for Invertible Logic

Abstract: Digital electronics are based on deterministic units called bits that can have one of two values, 0 and 1. New theoretical work suggests that circuits built out of probabilistic units that fluctuate randomly in value between 0 and 1 can be used to perform multiple functions: A multiplier, for example, can also function as a factorizer.

Fast, energy-efficient, robust, and reproducible mixed-signal neuromorphic classifier based on embedded NOR flash memory technology

Abstract: We have designed, fabricated, and tested a prototype mixed-signal, 28×28-binary-input, 10-ouput, 3-layer neuromorphic network based on embedded nonvolatile floating-gate cell arrays redesigned from a commercial 180-nm NOR flash memory. Each array performs a very fast and energy-efficient analog vector-by-matrix multiplication, which is the bottleneck for signal propagation in neuromorphic networks. All functional components of the prototype circuit, including 2 synaptic arrays with 101,780 floating-gate synaptic cells, 74 analog neurons, and the peripheral circuitry for weight adjustment and I/O operations, have a total area below 1 mm2. Its testing on the MNIST benchmark set has shown a classification fidelity of 94.65%, close to the 96.2% obtained in simulation. The classification of one pattern takes 103× better than those of the 28-nm IBM TrueNorth digital chip for the same task at a similar fidelity. Estimates show that this performance may be further improved using a better neuron design and a more advanced memory technology, leading to a >102x advantage in speed and a >104x advantage in energy efficiency over the state-of-the-art purely digital circuits for classification of large, complex patterns. Experimental results for the chip-to-chip statistics, long-term drift, and temperature sensitivity show no evident showstoppers on the way toward practical deep neuromorphic networks with unprecedented performance.

A scalable multi-core architecture with heterogeneous memory structures for Dynamic Neuromorphic Asynchronous Processors (DYNAPs)

Abstract: Neuromorphic computing systems comprise networks of neurons that use asynchronous events for both computation and communication. This type of representation offers several advantages in terms of bandwidth and power consumption in neuromorphic electronic systems. However, managing the traffic of asynchronous events in large scale systems is a daunting task, both in terms of circuit complexity and memory requirements. Here we present a novel routing methodology that employs both hierarchical and mesh routing strategies and combines heterogeneous memory structures for minimizing both memory requirements and latency, while maximizing programming flexibility to support a wide range of event-based neural network architectures, through parameter configuration. We validated the proposed scheme in a prototype multi-core neuromorphic processor chip that employs hybrid analog/digital circuits for emulating synapse and neuron dynamics together with asynchronous digital circuits for managing the address-event traffic. We present a theoretical analysis of the proposed connectivity scheme, describe the methods and circuits used to implement such scheme, and characterize the prototype chip. Finally, we demonstrate the use of the neuromorphic processor with a convolutional neural network for the real-time classification of visual symbols being flashed to a dynamic vision sensor (DVS) at high speed.

A Synthesis Methodology for Ternary Logic Circuits in Emerging Device Technologies

Abstract: Automatic synthesis of digital circuits has played a key role in obtaining high-performance designs. While considerable work has been done in the past, emerging device technologies call for a need to re-examine the synthesis approaches, so that better circuits that harness the true power of these technologies can be developed. This paper presents a methodology for synthesis applicable to devices that support ternary logic. We present an algorithm for synthesis that combines a geometrical representation with unary operators of multivalued logic . The geometric representation facilitates scanning appropriately to obtain simple sum-of-products expressions in terms of unary operators. An implementation based on Python is described. The power of the approach lies in its applicability to a wide variety of circuits. The proposed approach leads to the savings of 26% and 22% in transistor-count, respectively, for a ternary full-adder and a ternary content-addressable memory (TCAM) over the best existing designs. Furthermore, the proposed approach requires, on an average, less than 10% of the number of the transistors in comparison with a recent decoder-based design for various ternary benchmark circuits. Extensive HSPICE simulation results show roughly 92% reduction in power-delay product (PDP) for a $12\times 12$ TCAM and 60% reduction in PDP for a 24-ternary digit barrel shifter over recent designs.

Design and Applications of Approximate Circuits by Gate-Level Pruning

Abstract: Energy-efficiency is a critical concern for many systems, ranging from Internet of things objects and mobile devices to high-performance computers. Moreover, after 40 years of prosperity, Moore’s law is starting to show its economic and technical limits. Noticing that many circuits are over-engineered and that many applications are error-resilient or require less precision than offered by the existing hardware, approximate computing has emerged as a potential solution to pursue improvements of digital circuits. In this regard, a technique to systematically tradeoff accuracy in exchange for area, power, and delay savings in digital circuits is proposed: gate-level pruning (GLP). A CAD tool is build and integrated into a standard digital flow to offer a wide range of cost-accuracy tradeoffs for any conventional design. The methodology is first demonstrated on adders, achieving up to 78% energy-delay-area reduction for 10% mean relative error. It is then detailed how this methodology can be applied on a more complex system composed of a multitude of arithmetic blocks and memory: the discrete cosine transform (DCT), which is a key building block for image and video processing applications. Even though arithmetic circuits represent less than 4% of the entire DCT area, it is shown that the GLP technique can lead to 21% energy-delay-area savings over the entire system for a reasonable image quality loss of 24 dB. This significant saving is achieved thanks to the pruned arithmetic circuits, which sets some nodes at constant values, enabling the synthesis tool to further simplify the circuit and memory.

Programmable Spin Logic Based on Spin Hall Effect in a Single Device

Abstract: Spin logic devices, due to their programmability and nonvolatility, are deemed as an ideal building block for the next generation of electronics. Though several types of spin logic based on domain wall motion, spin-field-effect transistor and automata made of magnetic nanoparticles have been proposed, an architecture with scalability, energy efficiency and compatibility with current complementary metal-oxide-semiconductor technology is still in urgent demand. Here, it is experimentally demonstrated that the spin Hall effect in magnetic films with perpendicular anisotropy can be utilized to construct such a spin logic device. Five commonly used logic gates with nonvolatility in a single device are realized. This demonstration could pave the way towards application of spintronics in logic circuits as well as the memory industry in the near future and could even give birth to logic-in-memory computing architectures.

Carbon nanotube-based three-dimensional monolithic optoelectronic integrated system.

Abstract: Single material-based monolithic optoelectronic integration with complementary metal oxide semiconductor-compatible signal processing circuits is one of the most pursued approaches in the post-Moore era to realize rapid data communication and functional diversification in a limited three-dimensional space. Here, we report an electrically driven carbon nanotube-based on-chip three-dimensional optoelectronic integrated circuit. We demonstrate that photovoltaic receivers, electrically driven transmitters and on-chip electronic circuits can all be fabricated using carbon nanotubes via a complementary metal oxide semiconductor-compatible low-temperature process, providing a seamless integration platform for realizing monolithic three-dimensional optoelectronic integrated circuits with diversified functionality such as the heterogeneous AND gates. These circuits can be vertically scaled down to sub-30 nm and operates in photovoltaic mode at room temperature. Parallel optical communication between functional layers, for example, bottom-layer digital circuits and top-layer memory, has been demonstrated by mapping data using a 2 × 2 transmitter/receiver array, which could be extended as the next generation energy-efficient signal processing paradigm.

A Logic Circuit Design for Perfecting Memristor-Based Material Implication

Abstract: Memristor-based material implication (M-IMP) logic is popular with logic operations, which provides a possibility that memory is operated directly. However, there is a small limitation that memristor is not able to reach the lowest resistance in M-IMP. In this brief, the M-IMP limitation and its influence are analyzed briefly. In addition, a circuit structure that performs a stateful logic operation on memristor memory based on a nanocrossbar is proposed, which can perfect the M-IMP limitation and eliminate the influence. Moreover, we simulate the proposed circuit design and the simulation results verify the correctness of the analysis.

Single Event Effects mitigation with TMRG tool

Abstract: Single Event Effects (SEE) are a major concern for integrated circuits exposed to radiation. There have been several techniques proposed to protect circuits against radiation-induced upsets. Among the others, the Triple Modular Redundancy (TMR) technique is one of the most popular. The purpose of the Triple Modular Redundancy Generator (TMRG) tool is to automatize the process of triplicating digital circuits freeing the designer from introducing the TMR code manually at the implementation stage. It helps to ensure that triplicated logic is maintained through the design process. Finally, the tool streamlines the process of introducing SEE in gate level simulations for final verification.

Quantum--Classical Interface Based on Single Flux Quantum Digital Logic

Abstract: We describe an approach to the integrated control and measurement of a large-scale superconducting multiqubit circuit using a proximal coprocessor based on the Single Flux Quantum (SFQ) digital logic family. Coherent control is realized by irradiating the qubits directly with classical bitstreams derived from optimal control theory. Qubit measurement is performed by a Josephson photon counter, which provides access to the classical result of projective quantum measurement at the millikelvin stage. We analyze the power budget and physical footprint of the SFQ coprocessor and discuss challenges and opportunities associated with this approach.

Thwarting analog IC piracy via combinational locking

Abstract: With a relatively small number of components, analog ICs are much more vulnerable to piracy, and especially reverse engineering, than many digital ICs. However, analog IC security has received much less research attention than digital ICs. We introduce a combinational locking technique using configurable current mirror for analog IC protection. The locking circuit is designed by applying Satisfiability Modulo Theories. With the locking system, only a single key value can make analog IC operate properly while the other key values result in significant performance degradation or malfunction. Moreover, circuit output is not monotone function with respect to key values and thus systematic attack is difficult to be effective. Experimental results demonstrate that this technique can largely thwart analog IC piracy with limited overhead.

A nanocryotron comparator can connect single-flux-quantum circuits to conventional electronics

Abstract: Integration with conventional electronics offers a straightforward and economical approach to upgrading existing superconducting technologies, such as scaling up superconducting detectors into large arrays and combining single flux quantum (SFQ) digital circuits with semiconductor logic gates and memories However, direct output signals from superconducting devices (eg, Josephson junctions) are usually not compatible with the input requirements of conventional devices (eg, transistors) Here, we demonstrate the use of a single three-terminal superconducting-nanowire device, called the nanocryotron (nTron), as a digital comparator to combine SFQ circuits with mature semiconductor circuits such as complementary metal oxide semiconductor (CMOS) circuits Since SFQ circuits can digitize output signals from general superconducting devices and CMOS circuits can interface existing CMOS-compatible electronics, our results demonstrate the feasibility of a general architecture that uses an nTron as an interface to realize a 'super-hybrid' system consisting of superconducting detectors, superconducting quantum electronics, CMOS logic gates and memories, and other conventional electronics

Designed cell consortia as fragrance-programmable analog-to-digital converters

Abstract: Synthetic biology advances the rational engineering of mammalian cells to achieve cell-based therapy goals. Synthetic gene networks have nearly reached the complexity of digital electronic circuits and enable single cells to perform programmable arithmetic calculations or to provide dynamic remote control of transgenes through electromagnetic waves. We designed a synthetic multilayered gaseous-fragrance-programmable analog-to-digital converter (ADC) allowing for remote control of digital gene expression with 2-bit AND-, OR- and NOR-gate logic in synchronized cell consortia. The ADC consists of multiple sampling-and-quantization modules sensing analog gaseous fragrance inputs; a gas-to-liquid transducer converting fragrance intensity into diffusible cell-to-cell signaling compounds; a digitization unit with a genetic amplifier circuit to improve the signal-to-noise ratio; and recombinase-based digital expression switches enabling 2-bit processing of logic gates. Synthetic ADCs that can remotely control cellular activities with digital precision may enable the development of novel biosensors and may provide bioelectronic interfaces synchronizing analog metabolic pathways with digital electronics.

Design automation and design space exploration for quantum computers

Abstract: A major hurdle to the deployment of quantum linear systems algorithms and recent quantum simulation algorithms lies in the difficulty to find inexpensive reversible circuits for arithmetic using existing hand coded methods. Motivated by recent advances in reversible logic synthesis, we synthesize arithmetic circuits using classical design automation flows and tools. The combination of classical and reversible logic synthesis enables the automatic design of large components in reversible logic starting from well-known hardware description languages such as Verilog. As a prototype example for our approach we automatically generate high quality networks for the reciprocal 1/x, which is necessary for quantum linear systems algorithms.

Design of Efficient BCD Adders in Quantum-Dot Cellular Automata

Abstract: Among the emerging technologies recently proposed as alternatives to the classic CMOS, quantum-dot cellular automata (QCA) is one of the most promising solutions to design ultralow-power and very high speed digital circuits. Efficient QCA-based implementations have been demonstrated for several binary and decimal arithmetic circuits, but significant improvements are still possible if the logic gates inherently available within the QCA technology are smartly exploited. This brief proposes a new approach to design QCA-based BCD adders. Exploiting innovative logic formulations and purpose-designed QCA modules, computational speed significantly higher than existing counterparts is achieved without sacrificing either the occupied area or the cell count.

Characterization of radiation effects in 65 nm digital circuits with the DRAD digital radiation test chip

Abstract: A Digital RADiation (DRAD) test chip has been specifically designed to study the impact of Total Ionizing Dose (TID) (<1 Grad) and Single Event Upset (SEU) on digital logic gates in a 65 nm CMOS technology. Nine different versions of standard cell libraries are studied in this chip, basically differing in the device dimensions, Vt flavor and layout of the device. Each library has eighteen test structures specifically designed to characterize delay degradation and power consumption of the standard cells. For SEU study, a dedicated test structure based on a shift register is designed for each library. TID results up to 500 Mrad are reported.

Ultra dense vertical transport FET circuits

Abstract: Logic circuits, or logic gates, are disclosed comprising vertical transport field effect transistors and one or more active gates, wherein the number of C PP 's for the logic circuit, in isolation, is equal to the number of active gates. The components of the logic circuit can be present in at least three different vertical circuit levels, including a circuit level comprising at least one horizontal plane passing through a conductive element that provides an input voltage to the one or more gate structures and another conductive element that provides an output voltage of the logic circuit, and another circuit level that comprises a horizontal plane passing through a conductive bridge from the N output to P output of the field effect transistors. Such logic circuits can include single-gate inverters, two-gate inverters, NOR2 logic gates, and NAND3 logic gates, among other more complicated logic circuits.

Design of XOR/AND gate using 2D photonic crystal principle

Abstract: In this paper, an effective design of all-optical logic gates like XOR gate and AND gate is presented. The structure of these two logic gates is based on T-shape waveguide with optimized silica dielectric rod. Along with the two input ports which are essential for the required logical operation, an extra reference input port is used. These two logic gates can be used to construct for various combinational logic circuits, data bit comparison circuits, pattern matching, data encoding/decoding and different switching functions etc.

A 17.4-b Delta-Sigma Capacitance-to-Digital Converter for One-Terminal Capacitive Sensors

Abstract: In this brief, we present a capacitance-to-digital converter (CDC) for one-terminal capacitive sensors. The designed CDC implements a digital correction technique to reduce nonidealities and noises, such as the offset, 1/f noise, and power supply noise. This correction technique can also minimize effectively the complexity of the analog front-end circuit. All sensor functions, including analog circuits (delta-sigma CDC, bandgap reference, and voltage regulator) and digital logics (microprocessor, memories, and interface logics), are integrated into a single chip and occupy approximately 90% of the area. The chip is fabricated in a 0.18- $\mu\mbox{m}$ standard CMOS process, which does not have a deep n-well stage. The analog and digital circuits, including the digital input/output pads, must share the same substrate in this design. However, the measurement results demonstrate highly effective resolutions of 16 to 17.4 b, which are achieved with different conversion times.

Proof of principle of a three-input AND–INHIBIT–OR combinatorial logic gate array

Abstract: A designed molecule fluoresces according to a combinatorial logic circuit equivalent to wiring together three-input AND, three-input INHIBIT and two-input OR logic gates.

High Speed All-Optical Logic Gate Using QD-SOA and its Application

Abstract: The scheme to realize high-speed (~250 Gb/s) all-optical Boolean logic gates using semiconductor optical amplifiers with quantum-dot (QD-SOA) is introduced and analyzed in this review. Numerical si...

MEMS Logic Using Mixed-Frequency Excitation

Abstract: We present multi-function microelectromechanical systems (MEMS) logic device that can perform the fundamental logic gate AND, OR, universal logic gates NAND, NOR, and a tristate logic gate using mixed-frequency excitation. The concept is based on exciting combination resonances due to the mixing of two or more input signals. The device vibrates at two steady states: a high state when the combination resonance is activated and a low state when no resonance is activated. These vibration states are assigned to logical value 1 or 0 to realize the logic gates. Using ac signals to drive the resonator and to execute the logic inputs unifies the input and output wave forms of the logic device, thereby opening the possibility for cascading among logic devices. We found that the energy consumption per cycle of the proposed logic resonator is higher than those of existing technologies. Hence, integration of such logic devices to build complex computational system needs to take into consideration lowering the total energy consumption. [2017-0041]

Analysis of stochastic logic circuits in unipolar, bipolar and hybrid formats

Abstract: Implementations of polynomials and functions using stochastic logic have been of interest due to their low-area and high fault-tolerance properties In stochastic logic, numbers are represented using unary bit streams where each bit is of same weight If a number is represented in the range [0,1], the representation is referred to as unipolar The representation is referred as bipolar if the number lies in the range [−1, 1] Typically, inputs and outputs are in same format However, sometimes the input and output may be in different formats; these are referred as circuits using hybrid formats While analysis of unipolar stochastic logic circuits and bipolar logic circuits containing ex-or, ex-nor and multiplexors are well understood, the analysis of general bipolar stochastic logic circuits and hybrid logic circuits are not well understood This paper presents general approaches to compute outputs of bipolar and hybrid stochastic logic circuits It is shown that the analysis approach presented in this paper can form a basis for synthesis of stochastic logic circuits in bipolar and hybrid formats

A pNML Compact Model Enabling the Exploration of Three-Dimensional Architectures

Abstract: In nano magnetic logic (NML), single-domain nanomagnets enable logic operations. Binary information can be encoded thanks to its bistable magnetization. Many implementations are currently discussed in literature, among them one promising candidate is perpendicular-nano magnetic logic (pNML). It features several advantages like the controllability of the switching mechanism, the simplicity of design, and the natural predisposition of being integrated in three-dimensional (3-D) architectures. Here we show how this technology can be adopted in the design of 3-D logic architectures. Physical equations and quantities have been gathered from experimental demonstrations of pNML devices; formulas have then been fitted and implemented in VHDL (VHSIC Hardware Description Language). In this paper, we present an analysis of pNML circuits: initially a Multiplexer has been manufactured and characterized, then our compact model has been tested through simulations. Moreover, the MUX has adopted to design a generic n-bit accumulator. Our results demonstrate that the compact model makes it possible to perform fast simulations, while maintaining a fine level of accuracy. Thanks to its flexibility, novel materials, geometric variations, and other technological improvements can be easily integrated in order to be tested at circuit level. We anticipate our essay to be a starting point for the exploration of large 3-D digital circuits.

Modeling for Spin-FET and Design of Spin-FET-Based Logic Gates

Abstract: Spintronics-based devices and circuits attract massive research interest from both academia and industry A number of the devices and logic circuits have been proposed such as spin-based magnetic tunnel junction and all spin logic gate A fundamental spin-based device, spin field-effect transistor (spin-FET) is one of the most interesting spin-based devices to address the power issue of semiconductor transistors which is still a research focus In this paper, we first present an electrical model for the spin-FET based on both theoretical and experimental results The theories of spin injection and detection are considered by a current driver of the spin-FET Gate voltage modulation following Datta–Das theory is combined with the experimental results from several works of literature Afterward, through the dc analysis of two spin-FETs with different channel materials, we demonstrate that the channel using InAs is a better choice to make a feasible spin-FET The channel length is also optimized by the comparison of simulation results Finally, a local geometry spin-FET model suitable for logic design is implemented with Verilog-A language and integrated on Cadence platform Using our model, a low-power inverter is designed based on the concept of complementary spin-FET, and a logic circuit is proposed to implement AND and NOR logic functions Simulation results validate the behaviors of the logic circuits and availability of our model

Particle Computation: Complexity, Algorithms, and Logic

Abstract: We investigate algorithmic control of a large swarm of mobile particles (such as robots, sensors, or building material) that move in a 2D workspace using a global input signal (such as gravity or a magnetic field). We show that a maze of obstacles to the environment can be used to create complex systems. We provide a wide range of results for a wide range of questions. These can be subdivided into external algorithmic problems, in which particle configurations serve as input for computations that are performed elsewhere, and internal logic problems, in which the particle configurations themselves are used for carrying out computations. For external algorithms, we give both negative and positive results. If we are given a set of stationary obstacles, we prove that it is NP-hard to decide whether a given initial configuration of unit-sized particles can be transformed into a desired target configuration. Moreover, we show that finding a control sequence of minimum length is PSPACE-complete. We also work on the inverse problem, providing constructive algorithms to design workspaces that efficiently implement arbitrary permutations between different configurations. For internal logic, we investigate how arbitrary computations can be implemented. We demonstrate how to encode dual-rail logic to build a universal logic gate that concurrently evaluates and, nand, nor, and or operations. Using many of these gates and appropriate interconnects, we can evaluate any logical expression. However, we establish that simulating the full range of complex interactions present in arbitrary digital circuits encounters a fundamental difficulty: a fan-out gate cannot be generated. We resolve this missing component with the help of 2x1 particles, which can create fan-out gates that produce multiple copies of the inputs. Using these gates we provide rules for replicating arbitrary digital circuits.

Memristor-based nonvolatile synchronous flip-flop circuits

Abstract: Flip-flops are basic units for all kinds of sequential logic circuits and complex digital electronics systems, which can be used to store binary data owing to their two stable logic states 0 and 1. SR flip-flop and D flip-flop are widely employed in digital circuits as representative types of basic flip-flops. In this paper, logic circuits of nonvolatile synchronous SR flip-flop and D flip-flop are proposed, which utilize nanoscale memristors as the nonvolatile memory elements to store the information with different conductance states. The resistive switching property of memristors is well-suited for implementing trigger function in flip-flop circuits. Compared with traditional flip-flop ones, the proposed memristor-based SR flip-flop and D flip-flop have nonvolatile characteristic, which is suitable for occasions with unstable power supply. Meanwhile, the designed circuits provide experimental references for the development of digital circuit structures based on the feasibility of tight integration of memristors with CMOS circuitry.

Tribotronic triggers and sequential logic circuits

Abstract: In this paper, a floating-gate tribotronic transistor (FGTT) based on a mobile triboelectric layer and a traditional silicon-based field-effect transistor (FET) is proposed. In the FGTT, the triboelectric charges in the layer created by contact electrification can be used to modulate charge carrier transport in the transistor. Based on the FGTTs and FETs, a tribotronic negated AND (NAND) gate that achieves mechanical-electrical coupled inputs, logic operations, and electrical level outputs is fabricated. By further integrating tribotronic NAND gates with traditional digital circuits, several basic units such as the tribotronic S-R trigger, D trigger, and T trigger have been demonstrated. Additionally, tribotronic sequential logic circuits such as registers and counters have also been integrated to enable external contact triggered storage and computation. In contrast to the conventional sequential logic units controlled by electrical signals, contact-triggered tribotronic sequential logic circuits are able to realize direct interaction and integration with the external environment. This development can lead to their potential application in micro/nano-sensors, electromechanical storage, interactive control, and intelligent instrumentation.