Showing papers on "Digital electronics published in 2020"

Introduction to spin wave computing

Abstract: This paper provides a tutorial overview over recent vigorous efforts to develop computing systems based on spin waves instead of charges and voltages. Spin-wave computing can be considered a subfield of spintronics, which uses magnetic excitations for computation and memory applications. The Tutorial combines backgrounds in spin-wave and device physics as well as circuit engineering to create synergies between the physics and electrical engineering communities to advance the field toward practical spin-wave circuits. After an introduction to magnetic interactions and spin-wave physics, the basic aspects of spin-wave computing and individual spin-wave devices are reviewed. The focus is on spin-wave majority gates as they are the most prominently pursued device concept. Subsequently, we discuss the current status and the challenges to combine spin-wave gates and obtain circuits and ultimately computing systems, considering essential aspects such as gate interconnection, logic level restoration, input–output consistency, and fan-out achievement. We argue that spin-wave circuits need to be embedded in conventional complementary metal–oxide–semiconductor (CMOS) circuits to obtain complete functional hybrid computing systems. The state of the art of benchmarking such hybrid spin-wave–CMOS systems is reviewed, and the current challenges to realize such systems are discussed. The benchmark indicates that hybrid spin-wave–CMOS systems promise ultralow-power operation and may ultimately outperform conventional CMOS circuits in terms of the power-delay-area product. Current challenges to achieve this goal include low-power signal restoration in spin-wave circuits as well as efficient spin-wave transducers.

Digital Electronics and Analog Photonics for Convolutional Neural Networks (DEAP-CNNs)

Abstract: Convolutional Neural Networks (CNNs) are powerful and highly ubiquitous tools for extracting features from large datasets for applications such as computer vision and natural language processing. However, a convolution is a computationally expensive operation in digital electronics. In contrast, neuromorphic photonic systems, which have experienced a recent surge of interest over the last few years, propose higher bandwidth and energy efficiencies for neural network training and inference. Neuromorphic photonics exploits the advantages of optical electronics, including the ease of analog processing, and busing multiple signals on a single waveguide at the speed of light. Here, we propose a Digital Electronic and Analog Photonic (DEAP) CNN hardware architecture that has potential to be 2.8 to 14 times faster while using almost 25% less energy than current state-of-the-art graphical processing units (GPUs).

Digital Biologically Plausible Implementation of Binarized Neural Networks With Differential Hafnium Oxide Resistive Memory Arrays.

Abstract: The brain performs intelligent tasks with extremely low energy consumption. This work takes its inspiration from two strategies used by the brain to achieve this energy efficiency: the absence of separation between computing and memory functions and reliance on low-precision computation. The emergence of resistive memory technologies indeed provides an opportunity to tightly co-integrate logic and memory in hardware. In parallel, the recently proposed concept of a Binarized Neural Network, where multiplications are replaced by exclusive NOR (XNOR) logic gates, offers a way to implement artificial intelligence using very low precision computation. In this work, we therefore propose a strategy for implementing low-energy Binarized Neural Networks that employs brain-inspired concepts while retaining the energy benefits of digital electronics. We design, fabricate, and test a memory array, including periphery and sensing circuits, that is optimized for this in-memory computing scheme. Our circuit employs hafnium oxide resistive memory integrated in the back end of line of a 130-nm CMOS process, in a two-transistor, two-resistor cell, which allows the exclusive NOR operations of the neural network to be performed directly within the sense amplifiers. We show, based on extensive electrical measurements, that our design allows a reduction in the number of bit errors on the synaptic weights without the use of formal error-correcting codes. We design a whole system using this memory array. We show on standard machine learning tasks (MNIST, CIFAR-10, ImageNet, and an ECG task) that the system has inherent resilience to bit errors. We evidence that its energy consumption is attractive compared to more standard approaches and that it can use memory devices in regimes where they exhibit particularly low programming energy and high endurance. We conclude the work by discussing how it associates biologically plausible ideas with more traditional digital electronics concepts.

Analogue two-dimensional semiconductor electronics

Abstract: Digital electronics are ubiquitous in the modern world, but analogue electronics also play a crucial role in many devices and applications. Analogue circuits are typically manufactured using silicon as the active material. However, the desire for improved performance, new devices and flexible integration has—as for their digital counterparts—led to research into alternative materials, including the use of two-dimensional (2D) materials. Here, we show that operational amplifiers—a basic building block of analogue electronics—can be created using the 2D semiconductor molybdenum disulfide (MoS2) as the active material. The device is capable of stable operation with good performance, and we demonstrate its use in feedback circuits including inverting amplifiers, integrators, log amplifiers and transimpedance amplifiers. We also show that our 2D platform can be used to monolithically integrate an analogue signal preconditioning circuit with a MoS2 photodetector. An operational amplifier that uses the two-dimensional semiconductor molybdenum disulfide as the active material can be used to create complex analogue circuits, including inverters, integrators and amplifiers.

Time-Encoding Analog-to-Digital Converters: Bridging the Analog Gap to Advanced Digital CMOS-Part 1: Basic Principles

Abstract: The scaling of CMOS technology deep into the nanometer range has created challenges for the design of highperformance analog ICs The shrinking supply voltage and presence of mismatch and noise restrain the dynamic range, causing analog circuits to be large in area and have a high power consumption in spite of the process scaling Analog circuits based on time encoding [1], [2] and hybrid analog/digital signal processing [3] have been developed to overcome these issues Realizing analog circuit functionality with highly digital circuits results in more scalable design solutions that can achieve excellent performance This article reviews the basic principles of time encoding applied, in particular, to analog-to-digital converters (ADCs) based on voltage-controlled oscillators (VCOs), one of the most successful time-encoding techniques to date

Low-complexity QCA universal shift register design using multiplexer and D flip-flop based on electronic correlations

Abstract: Quantum-dot cellular automata (QCA) represent an alternative technology for implementing various computations and high-performance, low-power consumption digital circuits at nanoscale. Meanwhile, an universal shift register (USR) with guaranteed free position shift and parallel input and transfer of the stored bit value of the register is an essential element in the design of the circuit. Therefore, we propose an USR circuit based on QCA (QUSR) which can be configured by combining the shift register with a multiplexer (Mux) to select the function of the register. In this study, we propose a 2-to-1 Mux based on the electronic correlations between the cells, and then extend this to a 4-to-1 Mux. We also propose a new D flip-flop, and design a shift register by connecting these. Finally, we propose a QUSR with an extremely optimized area and latency, by connecting four 4-to-1 Muxes and a four-bit shift register. The proposed QUSR is highly efficient, in terms of the space, time complexity and energy dissipation. All proposed structures are simulated by QCADesigner to demonstrate the clarity of the motion and efficiency. We also measured and compared the energy dissipation in three tunneling levels by QCAPro.

Programmable metamaterials with digital synthetic impedance circuits for vibration control

Abstract: This paper studies a new type of smart metamaterial consisting of piezoelectric actuators and digital synthetic impedance circuits (digital circuits). The digital circuit contains a micro-controller. By programming the micro-controller, the circuit can establish any desired impedance between the terminals of the connected piezoelectric patch, therefore to program the dynamical behaviors of the designed metamaterial. In this sense, a programmable metamaterial is studied. Experiments are conducted to study its programmable dynamical behaviors, with a particular focus on vibration reduction. Numerical simulations are also done in this work to qualitatively verify the experimental results. Different design methods are used to customize the dynamical behaviors of the designed metamaterial. Results demonstrate that the proposed smart metamaterial can be flexibly programmed online to reduce vibration at desired frequencies or within a large frequency band. The proposed programmable metamaterial conception can be naturally extended to other kinds of structures like plates and shells, they are promising components in the future adaptive structures.

A Semiparallel Full-Adder in IMPLY Logic

Abstract: Passive implementation of memristors has led to several innovative works in the field of electronics. Despite being primarily a candidate for memory applications, memristors have proven to be beneficial in several other circuits and applications as well. One of the use cases is the implementation of digital circuits such as adders. Among several logic implementations using memristors, IMPLY logic is one of the promising candidates. In this brief, we present a new architecture for a digital full-adder, which is up to 41% faster than existing IMPLY-based serial designs while requiring up to 78% less area (memristors) compared to the existing parallel design.

Full Adder Circuit Design with Novel Lower Complexity XOR Gate in QCA Technology

Abstract: Quantum-dot Cellular Automata (QCA) is a new technology for designing digital circuits in Nanoscale. This technology utilizes quantum dots rather than diodes and transistors. QCA supplies a new computation platform, where binary data can be represented by polarized cells, which can define by the electron’s configurations inside the cell. This paper explains QCA based combinational circuit design; such as half-adder and full-adder, by only one uniform layer of cells. The proposed design is accomplished using a novel XOR gate. The proposed XOR gate has a 50% speed improvement and 35% reduction in the number of cells needed over the best reported XOR. The results of QCADesigner software show that the proposed designs have less complexity and less power consumption than previous designs.

Vesti: Energy-Efficient In-Memory Computing Accelerator for Deep Neural Networks

Abstract: To enable essential deep learning computation on energy-constrained hardware platforms, including mobile, wearable, and Internet of Things (IoT) devices, a number of digital ASIC designs have presented customized dataflow and enhanced parallelism. However, in conventional digital designs, the biggest bottleneck for energy-efficient deep neural networks (DNNs) has reportedly been the data access and movement. To eliminate the storage access bottleneck, new SRAM macros that support in-memory computing have been recently demonstrated. Several in-SRAM computing works have used the mix of analog and digital circuits to perform XNOR-and-ACcumulate (XAC) operation without row-by-row memory access and can map a subset of DNNs with binary weights and binary activations. In the single array level, large improvement in energy efficiency (e.g., two orders of magnitude improvement) has been reported in computing XAC over digital-only hardware performing the same operation. In this article, by integrating many instances of such in-memory computing SRAM macros with an ensemble of peripheral digital circuits, we architect a new DNN accelerator, titled Vesti . This new accelerator is designed to support configurable multibit activations and large-scale DNNs seamlessly while substantially improving the chip-level energy-efficiency with favorable accuracy tradeoff compared to conventional digital ASIC. Vesti also employs double-buffering with two groups of in-memory computing SRAMs, effectively hiding the row-by-row write latencies of in-memory computing SRAMs. The Vesti accelerator is fully designed and laid out in 65-nm CMOS, demonstrating ultralow energy consumption of $ for CIFAR-10 classification at 1.0-V supply.

Design of an Efficient N × N Butterfly Switching Network in Quantum-Dot Cellular Automata (QCA)

Abstract: Quantum-dot cellular automata (QCA) is a rapidly growing nanotechnology very well suited for designing ultra-dense, low-power, and high-performance digital circuits. In parallel computing, the multistage interconnection network (MIN) provides maximum bandwidth to the components and minimum latency access to the memory modules. Much research has been conducted on CMOS-based MINs for parallel computing. However, the QCA-based switching network is still underexplored. This article proposes a QCA architecture of a new single-layer butterfly switching network (BSN). To achieve this, we design an efficient 2 × 2 switching element (SE), using a modified majority ( $\mathcal{M}{_{[x,y]}}$ ) gate that is fully utilized (i.e., no fixed logic like “0” and “1” at the inputs). The use of a fully utilized majority gate over a partially utilized majority (PUM) one makes the proposed SE more cost-efficient and versatile, and therefore it is used as the building block for designing the switching network. In addition, we deploy the SE to realize 4 × 4 and 8 × 8 BSNs. We also show how the design can be extended for an N × N BSN. All the proposed circuits have been modeled and verified by QCADesigner. QCAPro is used for estimating the average switching and leakage energy dissipation of the proposed circuits. The results show considerable enhancement in terms of cell count, device area, and latency, and thereby outperform all reported prior designs.

Regulated Charge Pumps: A Comparative Study by Means of Verilog-AMS

Abstract: This paper proposes a comparative study of regulation schemes for charge-pump-based voltage generators using behavioral models in Verilog- Analog Mixed Signal (AMS) code. An accurate and simple model of the charge pump is first introduced. It allows reducing the simulation time of complex electronic systems made up by both analog and digital circuits while maintaining a good agreement with transistor-level simulations. Finally, a comprehensive comparative study of the different regulation schemes for charge pumps is reported which allows the designer to choose the most suitable topology for a given application and Charge Pump (CP) operative zone.

Ultra-Low-Power FDSOI Neural Circuits for Extreme-Edge Neuromorphic Intelligence

Abstract: Recent years have seen an increasing interest in the development of artificial intelligence circuits and systems for edge computing applications In-memory computing mixed-signal neuromorphic architectures provide promising ultra-low-power solutions for edge-computing sensory-processing applications, thanks to their ability to emulate spiking neural networks in real-time The fine-grain parallelism offered by this approach allows such neural circuits to process the sensory data efficiently by adapting their dynamics to the ones of the sensed signals, without having to resort to the time-multiplexed computing paradigm of von Neumann architectures To reduce power consumption even further, we present a set of mixed-signal analog/digital circuits that exploit the features of advanced Fully-Depleted Silicon on Insulator (FDSOI) integration processes Specifically, we explore the options of advanced FDSOI technologies to address analog design issues and optimize the design of the synapse integrator and of the adaptive neuron circuits accordingly We present circuit simulation results and demonstrate the circuit's ability to produce biologically plausible neural dynamics with compact designs, optimized for the realization of large-scale spiking neural networks in neuromorphic processors

Noisy Machines: Understanding noisy neural networks and enhancing robustness to analog hardware errors using distillation

Abstract: The success of deep learning has brought forth a wave of interest in computer hardware design to better meet the high demands of neural network inference. In particular, analog computing hardware has been heavily motivated specifically for accelerating neural networks, based on either electronic, optical or photonic devices, which may well achieve lower power consumption than conventional digital electronics. However, these proposed analog accelerators suffer from the intrinsic noise generated by their physical components, which makes it challenging to achieve high accuracy on deep neural networks. Hence, for successful deployment on analog accelerators, it is essential to be able to train deep neural networks to be robust to random continuous noise in the network weights, which is a somewhat new challenge in machine learning. In this paper, we advance the understanding of noisy neural networks. We outline how a noisy neural network has reduced learning capacity as a result of loss of mutual information between its input and output. To combat this, we propose using knowledge distillation combined with noise injection during training to achieve more noise robust networks, which is demonstrated experimentally across different networks and datasets, including ImageNet. Our method achieves models with as much as two times greater noise tolerance compared with the previous best attempts, which is a significant step towards making analog hardware practical for deep learning.

Configurable Logic Blocks and Memory Blocks for Beyond-CMOS FPGA-Based Embedded Systems

Abstract: Field programmable gate arrays (FPGAs)-based embedded systems are easy to implement, reconfigure, test, and validate. Configurable logic blocks (CLBs) and memory blocks are the building blocks of FPGA. The rising issues in CMOS fabrication at smaller nanometer levels has increased the need for beyond-CMOS technologies to build complex circuits at extremely smaller nanometer levels. Quantum-dot cellular automata (QCA) is a nascent beyond-CMOS nanotechnology technique to design low-power and high-performance digital circuits. In this letter, a layout strategy is proposed to design QCA circuits. Using the proposed strategy, novel and cost-efficient designs of CLBs and memory blocks are proposed. The proposed blocks can be used to develop FPGA architecture and FPGA-based embedded systems in QCA. The proposed circuits are cost effective and perform better than many state-of-the-art designs. Simulation and verification are done in QCADesigner using coherence vector simulation engine.

Area Optimization of CMOS Full Adder Design Using 3T XOR

Abstract: GDI (Gate Diffusion Input) is a new technique of low power digital circuit design is proposed. This technique allows minimization of area and power consumption of digital circuits. In this design XOR gate is designed using 3 transistors and CMOS full adder is designed based on two 3T XOR and one 2T Mux. Using 8 transistors the full adder is designed in this paper and voltage scaling also done by reducing supply voltage. In this proposed full adder, the power consumption 4.604µW is achieved and the total area is 144µm2.

In-Hardware Training Chip Based on CMOS Invertible Logic for Machine Learning

Abstract: Deep Neural Networks (DNNs) have recently shown state-of-the-art results on various applications, such as computer vision and recognition tasks. DNN inference engines can be implemented in hardware with high energy efficiency as the computation can be realized using a low-precision fixed point or even binary precision with sufficient cognition accuracies. On the other hand, training DNNs using the well-known back-propagation algorithm requires high-precision floating-point computations on a CPU and/or GPU causing significant power dissipation (more than hundreds of kW) and long training time (several days or more). In this paper, we demonstrate a training chip fabricated using a commercial 65-nm CMOS technology for machine learning. The chip performs training without back propagation by using invertible logic with stochastic computing that can directly obtain weight values using input/output training data with low precision suitable for inference. When training neurons that compute the weighted sum of all inputs and then apply a non-linear activation function, our chip demonstrates a reduction of power dissipation and latency by 99.98% and 99.95%, respectively, in comparison with a state-of-the-art software implementation.

Cryo-CMOS for Analog/Mixed-Signal Circuits and Systems

Abstract: CMOS circuits operating at cryogenic temperature (cryo-CMOS) are required in several low-temperature applications. A compelling example is the electronic interface for quantum processors, which must reside very close to the cryogenic quantum devices it serves, and hence operate at the same temperature, so as to enable practical large-scale quantum computers. Such cryo-CMOS circuits must achieve extremely high performance while dissipating minimum power to be compatible with existing cryogenic refrigerators. These requirements asks for cryo-CMOS electronics on par with or even exceeding their room-temperature counterparts. This paper overviews the challenges and the opportunities in designing cryo-CMOS circuits, with a focus on analog and mixed-signal circuits, such as voltage references and data converters.

Designing a DDS-Based SoC for High-Fidelity Multi-Qubit Control

Abstract: The design of a large-scale quantum computer requires co-optimization of both the quantum bits (qubits) and their control electronics. This work presents the first systematic design of such a controller to simultaneously and accurately manipulate the states of multiple spin qubits or transmons. By employing both analytical and simulation techniques, the detailed electrical specifications of the controller have been derived for a single-qubit gate fidelity of 99.99% and validated using a qubit Hamiltonian simulator. Trade-offs between several architectures with different levels of digitization are discussed, resulting in the selection of a highly digital DDS-based solution. Initiating from the system specifications, a complete error budget for the various analog and digital circuit blocks is drafted and their detailed electrical specifications, such as signal power, linearity, spurs and noise, are derived to obtain a digital-intensive power-optimized multi-qubit controller. A power consumption estimate demonstrates the feasibility of such a system in a nanometer CMOS technology node. Finally, application examples, including qubit calibration and multi-qubit excitation, are simulated with the proposed controller to demonstrate its efficacy. The proposed methodology, and more specifically, the proposed error budget lay the foundations for the design of a scalable electronic controller enabling large-scale quantum computers with practical applications.

Parity-preserving reversible flip-flops with low quantum cost in nanoscale

Abstract: In recent years, reversible logic has attracted high importance because of its in-cognitive property of reduction in energy dissipation which is the main requirement in low-power digital circuits. Reversible logic is one of emerging fields of research, which is used in various fields such as low-power CMOS, DNA computing, quantum computing, fault tolerance and nanotechnology. A circuit is reversible if it has the same number of inputs and outputs, and there is a one-to-one correspondence between them. A reversible circuit is parity-preserving if the EXOR of the inputs is equal to the EXOR of the outputs. Flip-flops are considered as one of the most important digital designs that are widely used as building blocks in the design of sequential circuits. In this paper, two new 4 × 4 parity-preserving reversible blocks are first proposed, called PNM1 and PNM2, respectively. Quantum syntheses of the proposed blocks are carried out using the Miller et al. method. In the following, effective designs of parity-preserving reversible D, T and J-K flip-flops along with their master–slave versions are introduced using the proposed parity-preserving reversible blocks and DFG gates. Finally, a 4-bit asynchronous up-counter is designed using the proposed parity-preserving reversible D flip-flop and FRG gate. The results of the comparisons show that although the proposed structures are close to previous designs in terms of gate count, constant input and garbage output criteria, they are superior in terms of quantum cost.

Discrete space optical signal processing

Abstract: As digital circuits are approaching the limits of Moore’s law, a great deal of effort has been directed to alternative computing approaches. Among them, the old concept of optical signal processing (OSP) has attracted attention, revisited in the light of metamaterials and nano-photonics. This approach has been successful in realizing basic mathematical operations, such as derivatives and integrals, but it is difficult to be applied to more complex ones. Here, inspired by digital filters, we propose a radically new OSP approach, able to realize arbitrary mathematical operations over a nano-photonic platform. Our concept consists in first sampling an optical signal in space through an array of optical antennas and then realizing the desired mathematical operation in discrete space through a network with a discrete number of input and output ports. The design of such network boils down to the design of a structure with a given scattering matrix, which for arbitrarily complex operations can be accomplished through inverse design algorithms. We demonstrate this concept for the case of spatial differentiation through a heuristic design based on a waveguide with periodic arrays of input/output channels at its opposite walls. Our approach combines the robustness and generality of traditional Fourier-based OSP with the compactness of nano-photonics and has the potential of transforming the design of OSP systems with applications in image processing and analog computing.

A Digital Closed-Loop Sense MEMS Disk Resonator Gyroscope Circuit Design Based on Integrated Analog Front-end.

Abstract: A digital closed-loop system design of a microelectromechanical systems (MEMS) disk resonator gyroscope (DRG) is proposed in this paper. Vibration models with non-ideal factors are provided based on the structure characteristics and operation mode of the sensing element. The DRG operates in force balance mode with four control loops. A closed self-excited loop realizes stable vibration amplitude on the basis of peak detection technology and phase control loop. Force-to-rebalance technology is employed for the closed sense loop. A high-frequency carrier loaded on an anchor weakens the effect of parasitic capacitances coupling. The signal detected by the charge amplifier is demodulated and converted into a digital output for subsequent processing. Considering compatibility with digital circuits and output precision demands, a low passband sigma-delta (ΣΔ) analog-to-digital converter (ADC) is implemented with a 111.8dB signal-to-noise ratio (SNR). The analog front-end and digital closed self-excited loop is manufactured with a standard 0.35 µm complementary metal-oxide-semiconductor (CMOS) technology. The experimental results show a bias instability of 2.1 °/h and a nonlinearity of 0.035% over the ± 400° full-scale range.

A New Class of Digital Circuits for the Design of Entropy Sources in Programmable Logic

Abstract: We propose a novel class of Digital Nonlinear Oscillators (DNOs) supporting complex dynamics, including chaos, suitable for the definition of high-performance and low-complexity entropy sources in Programmable Logic Devices (PLDs). We derive our proposal from the analysis of simplified models, investigated as non-autonomous nonlinear dynamical systems under different excitation conditions. The study lead the authors to the design of a fully digital entropy source consuming only two slices of a Xilinx FPGA, including post-processing, sufficient to define a class of TRNGs capable to pass the NIST standard tests for randomness in any worst case experimentally tested by the authors (6 chips, 96 generators). The solution has been compared with others published in the literature, confirming the validity of the proposal.

Compact Source-Gated Transistor Analog Circuits for Ubiquitous Sensors

Abstract: Silicon-based digital electronics have evolved over decades through an aggressive scaling process following Moore’s law with increasingly complex device structures. Simultaneously, large-area electronics have continued to rely on the same field-effect transistor structure with minimal evolution. This limitation has resulted in less than ideal circuit designs, with increased complexity to account for shortcomings in material properties and process control. At present, this situation is holding back the development of novel systems required for printed and flexible electronic applications beyond the Internet of Things. In this work we demonstrate the opportunity offered by the source-gated transistor’s unique properties for low-cost, highly functional large-area applications in two extremely compact circuit blocks. Polysilicon common-source amplifiers show 49 dB gain, the highest reported for a two-transistor unipolar circuit. Current mirrors fabricated in polysilicon and InGaZnO have, in addition to excellent current copying performance, the ability to control the temperature dependence (degrees of positive, neutral or negative) of output current solely by choice of relative transistor geometry, giving further flexibility to the design engineer. Application examples are proposed, including local amplification of sensor output for improved signal integrity, as well as temperature-regulated delay stages and timing circuits for homeostatic operation in future wearables. Numerous applications will benefit from these highly competitive compact circuit designs with robust performance, improved energy efficiency and tolerance to geometrical variations: sensor front-ends, temperature sensors, pixel drivers, bias analog blocks and high-gain amplifiers.

High performance 2:1, 4:1 and 8:1 binary and ternary multiplexer realization using cntfet technology

Abstract: In the world of integrated circuits, CMOS has lost its accreditation during scaling beyond 32nm. The main drawbacks of using CMOS transistors are high power consumption and high leakage current. Scaling causes severe Short Channel Effects (SCE) which are difficult to overcome. CNTFET technologies modify these limitations by providing a stronger control over a thin silicon body. CNTFET device has a higher controllability, resulting relatively high on/off ratio. CNTFET devices can be used to increase the performance by reducing the leakage current and power dissipation. Carbon Nanotube Field Effect Transistor (CNTFET), one of nano electronic devices, is a transistor with its channel made of carbon Nanotube. CNTFET based devices offer high mobility for near-sensible transport, high carrier velocity for fast switching, as well as better electrostatic control due to the one-dimensional structure of CNTs. CNTFET is preferred over Si-MOSFET for logic design due to its magnificent thermal, mechanical and electrical properties. Now a days, low power and low energy have become an important issue in consumer electronics and it is necessary to do research in combinational circuits. One of the important elements in digital circuits is a multiplexer or data selector for processing multiple inputs with a single output. In this abstract, the different designs of multiplexer using CNTFET logic are analysed. CNTFET logic is one of the auspicious opportunity to conventional binary logic, since it is possible to achieve simplicity and low power dissipation due to the reduced circuit such as interconnects and chip area. This paper presents a design methodology which uses the combination of Binary multiplexers and Ternary multiplexers.

Memristor-CNTFET based Ternary Full Adders

Abstract: Recently multilevel systems are one of the hottest topics in the digital electronics field. Multi-level logic (MVL) overcomes the issues of interconnections. The ternary system is a promising system where the implementation complexity is low and more information can be stored compared to the binary logic system. In this paper, 4-bit adder has been implemented with CNTFETs and memristors using three different methods; carry-ripple adder, carry-skip adder and carry-lookahead adder. A comparative study between the three adders is introduced in terms of the average power and delay. The adders have been validated with SPICE simulations using VTEAM memristor and Stanford CNTFET transistor models. The carry-lookahead adder (CLA) shows 10x better power-delay product compared to carry ripple and carry-skip adders. The power and temperature variations are studied on the designed circuits.

Circuit-Level Techniques for Logic and Memory Blocks in Approximate Computing Systemsx

Abstract: This article presents an overview of circuit-level techniques used for approximate computing (AC), including both computation and data storage units. After providing some background concept and methodology review, this article proceeds to provide a detailed review of prior art in circuit-level approximation techniques for data path and memory. The focus is on identifying key circuit-level approximation techniques that are applicable to the computational blocks in general and for both volatile and nonvolatile memory circuit technologies. Emphasis is also placed on the error metrics used to assess the output quality of approximate compute and memory units and whether the accuracy setting is dynamically reconfigurable. This article is concluded with a summary of the key distinguishing features of the reviewed prior art.

A Faithful Binary Circuit Model

Abstract: Fugger et al. (2016) proved that no existing digital circuit model, including those based on pure and inertial delay channels, faithfully captures glitch propagation: for the short-pulse filtration (SPF) problem similar to that of building a one-shot inertial delay, they showed that every member of the broad class of bounded single-history channels either contradicts the unsolvability of SPF in bounded time or the solvability of SPF in unbounded time in physical circuits. In this article, we propose binary circuit models based on novel involution channels that do not suffer from this deficiency. Namely, in sharp contrast to bounded single-history channels, SPF cannot be solved in bounded time with involution channels, whereas it is easy to provide an unbounded SPF implementation. Hence, binary-valued circuit models based on involution channels allow to solve SPF precisely when this is possible in physical circuits. Additionally, using both SPICE simulations and physical measurements of an inverter chain instrumented by high-speed analog amplifiers, we demonstrate that our model provides good modeling accuracy with respect to real circuits as well. Consequently, our involution channel model is not only a promising basis for sound formal verification but also allows to seamlessly improve existing dynamic timing analysis.