Showing papers on "Digital electronics published in 2021"

Re-Thinking Analog Integrated Circuits in Digital Terms: A New Design Concept for the IoT Era

Abstract: A steady trend towards the design of mostly-digital and digital-friendly analog circuits, suitable to integration in mainstream nanoscale CMOS by a highly automated design flow, has been observed in the last years to address the requirements of the emerging Internet of Things (IoT) applications. In this context, this tutorial brief presents an overview of concepts and design methodologies that emerged in the last decade, aimed to the implementation of analog circuits like Operational Transconductance Amplifiers, Voltage References and Data Converters by digital circuits. The current design challenges and application scenarios as well as the future perspectives and opportunities in the field of digital-based analog processing are finally discussed.

QECOOL: On-Line Quantum Error Correction with a Superconducting Decoder for Surface Code

Abstract: Due to the low error tolerance of a qubit, detecting and correcting errors on it is essential for fault-tolerant quantum computing. Surface code (SC) associated with its decoding algorithm is one of the most promising quantum error correction (QEC) methods. QEC needs to be very power-efficient since the power budget is limited inside of a dilution refrigerator for superconducting qubits by which one of the most successful quantum computers (QCs) is built. In this paper, we propose an online-QEC algorithm and its hardware implementation with SFQ based superconducting digital circuits. We design a key building block of the proposed hardware with an SFQ cell library and evaluate it by the SPICE-level simulation. Each logic element is composed of about 3000 Josephson junctions and power consumption is about $2.78 \mu \mathrm{W}$ when operating with 2 GHz clock frequency which meets the required decoding speed. Our decoder is simulated on a quantum error simulator for code distances 5 to 13 and achieves a 1.0% accuracy threshold.

A New Nano Design for Implementation of a Digital Comparator Based on Quantum-Dot Cellular Automata

Abstract: Quantum-dot is the result of elastic relaxation which has a straight relationship with the optical and electronic aspects of the quantum-dot-based devices. In nanotechnologies, Quantum-dot Cellular Automata (QCA) is a perfect transistor-less computation method where it tries to create general computation at the nanoscale with better switching frequency and enhanced scale integration to overcome the scaling shortfalls of CMOS technology. In this technology, binary information is represented based on the distribution of electron configuration in chemical molecules. Also, the comparator is the essential component in digital circuits, which takes two binary numbers as input and implements their resemblance. In this paper, a 1-bit comparator architecture in an optimized and efficient manner is suggested to bring a new phase of comparator circuit based on QCA, and then a novel 2-bit comparator structure is offered. The simulation and functionality of proposed comparators have been examined by the QCAdesigner tool, and comparison with formerly designs shows a high degree of compactness and consistent performance of proposed designs. Proposed 1-bit and 2-bit QCA comparators exhibit a delay of 0.75 and 2.75 clock cycle, occupy an active area of 0.04 and 0.19 μm2, and use 31 and 125 QCA cells, respectively.

Monolithically Integrated GaN Ring Oscillator Based on High-Performance Complementary Logic Inverters

Abstract: A gallium nitride (GaN) ring oscillator based on high-performance one-chip complementary logic (CL) inverters is demonstrated on a conventional ${p}$ -GaN gate power HEMT (high-electron-mobility transistor) platform. It manifests the feasibility of the multiple-stage monolithic integration of GaN CL gates, the most energy-efficient digital circuit configuration, and consequently the potential of deploying CL circuits in the all-GaN power integration as peripheral circuits with higher energy efficiency. Thanks to the successful monolithic integration of enhancement-mode ${p}$ -channel and ${n}$ -channel field-effect transistors, the integrated CL inverters in this work present remarkable performances, including stringent rail-to-rail operations, substantially suppressed static power dissipation at both logic ‘low’ and ‘high’ states, suitable transition threshold voltages of ~2.0 V (40% of the common 5-V supply) and wide noise margins above 1.8 V (36% of 5 V).

Passive Digital Sensing Method and Its Implementation on Passive RFID Temperature Sensors

Abstract: Benefitting from the advancement of digital electronics in the 20th century, sensors have also gradually evolved from analog to digital. As semiconductor components are required in digital sensors, a power supply is still needed for the sensor. To eliminate the need for a power supply a concept of passive digital sensing is proposed. Different from the semiconductor-based electrical digital sensing method, the parameter to be measured is first converted to a mechanical signal, then the mechanical signal is encoded to multiple digital bits by a passive digitizer, where each bit is identified as open or short state that is detectable by general IO ports. To demonstrate the proposed sensing concept, a passive RFID temperature sensor is implemented using a bimetallic coil as the temperature sensing unit. The 6-bit binary codes are acquired and transmitted by a passive RFID that is powered by an energy harvester. The test results show that the temperature sensor has a measurement sensitivity of 1.32 °C/bit and a working distance over 10 meters.

Heterojunction Negative-Capacitance Tunnel-FET as a Promising Candidate for Sub-0.4V V DD Digital Logic Circuits

Abstract: The objective of this paper is to exemplify the significant improvements achieved in speed and power-consumption by utilizing negative-capacitance Tunnel FETs in sub-0.4 VDD digital logic applications. A heterojunction negative-capacitance TFET (NCTFET) has been designed using SILVACO TCAD and its accuracy demonstrated by properly fitting the simulated polarization data with calculated L-K equation solution. The prospects of the proposed structure have been manifested in the steep average subthreshold-slope of 27mV/decade over 9 decades of current and high ION/IOFF of 1016, possible due to the internal voltage amplification and voltage pinning effects. The device has been suitably implemented in inverter, ring-oscillator, 2:1 multiplexer and Full-Adder circuits and benchmarked in delay and power-consumption with a reference TFET (R-TFET) and previously proposed structures. The effect of varying thickness of ferroelectric material on the circuit-level performance has also been discussed. Furthermore, the NCTFET has been implemented in a 6-T SRAM which successfully demonstrates the effect of tFE on noise margin and read-write delay, operated at 0.4 VDD. The proposed NCTFET has been presented and justified as a promising candidate for high-speed and low power digital circuits.

Design and analysis of novel QCA full adder-subtractor

Abstract: Quantum-dot Cellular Automata is an evolving post-CMOS paradigm that can be used for designing nanoscale circuits. Digital circuits are implemented in QCA using majority logic. Adder and subtractor...

Implementation of Reversible Logic Gates with Quantum Gates

Abstract: Quantum is an emerging technology in future computers. Reversibility is the main advantage of quantum computers. In conventional computers, the computation is irreversible i.e. the input bits are lost once the logic block generates the output and input bits cannot be restored but it can be done in reversible computation because in reversible computation the inputs and outputs have a one-to-one correspondence. Therefore, a reversible gate input could even be uniquely determined from their output which leads to less power consumption. Hence the complexity of the digital circuits can be reduced by using reversible computing. In quantum computer to perform reversible operations, we need to implement the reversible gates using quantum gates. In this paper, we discussed various reversible logic gates like Feynman, Toffoli, R, Peres and TR gates using basic quantum gates like CNOT, Pauli, Swap gates and their implementation using IBM quantum experience.

Design and Verification of SFQ Cell Library for Superconducting LSI Digital Circuits

Abstract: We have developed a cell library for superconducting large scale integrated (LSI) digital circuits based on Single Flux Quantum (SFQ) devices. The circuits were designed for a 6-kA/cm2 Nb/AlOx/Nb junction process with 10 mask levels including one ground plane and two Nb wiring layers. The initial design and optimization of the circuit parameters were achieved by means of the optimization functions in a circuit simulator, PSCAN2, to ensure that important circuit parameters, Josephson critical current ( IC ), bias current ( Ibias ), and inductance satisfied minimal margin requirements. Critical margins of IC and Ibias were then further improved manually. To compensate the scattering in the circuit parameters from fabrication by design as much as possible, the critical junction parameters were optimized to further centralize the IC . The library cells were laid out following our design rules determined by systematic experiments on process control monitors (PCM). Basic cells including Josephson transmission lines, splitters, confluence buffers, D flip-flops, T flip-flops, and XOR and NDRO gates were designed, fabricated, and successfully tested at low frequencies. Wide overlaps of the operating regions for the common bias voltages were confirmed.

A New Design of a Carry-Save Adder Based on Quantum-Dot Cellular Automata

Abstract: Quantum-dot cellular automata (QCA) technology has been known as an appropriate paradigm for implementing low power consumption digital circuits and different high-performance computations at nanoscale. Considering its nature, this technology has shallow energy losses. Besides, an adder is one of the main parts in the digital circuit designs. Moreover, full adder circuits are the basic units in the digital logic and arithmetic circuits. An emerging three-layer four-bit QCA-based carry-save adder (CSA) circuit is presented in this article. The proposed design offers good performance regarding the delay, area size, and cell number compared to existing ones. The suggested four-bit QCA-based CSA circuit has been depending on a new dedicated QCA full adder circuit. The proposed architectures are simulated with the utilization of the QCADesigner tool version 2.0.3. The outcomes of the simulation have proven that the improved circuit provides a significant development for cell number and area possession compared to previous single-layer and multilayer circuits, and the design leads to around 33.9% improvement in cell number in comparison with the best-presented QCA-based CSA design. Moreover, the proposed CSA architecture utilizes 347 QCA cells.

Designing a New 4:2 Compressor Using an Efficient Multi-Layer Full-Adder Based on Nanoscale Quantum-Dot Cellular Automata

Abstract: Quantum-dot Cellular Automata (QCA) is novel prominent nanotechnology. It promises a substitution to Complementary Metal–Oxide–Semiconductor (CMOS) technology with a higher scale integration, smaller size, faster speed, higher switching frequency, and lower power consumption. It also causes digital circuits to be schematized with incredible velocity and density. The full adder, compressor, and multiplier circuits are the basic units in the QCA technology. Compressors are an important class of arithmetic circuits, and researchers can use quantum compressors in the structure of complex systems. In this paper, first, a novel three-input multi-layer full-adder in QCA technology is designed, and based on it, a new multi-layer 4:2 compressor is presented. The proposed QCA-based full-adder and compressor uses an XOR gate. The proposed design offers good performance regarding the delay, area size, and cell number comparing to the existing ones. Also, in this gate, the output signal is not enclosed, and we can use it easily. The accuracy of the suggested circuits has been assessed with the utilization of QCADesigner 2.0.3. The results show that the proposed 4:2 compressor architecture utilizes 75 cell and 1.25 clock phases, which are efficient than other designs.

A survey of digital circuit testing in the light of machine learning

Abstract: The insistent trend in today's nanoscale technology, to keep abreast of the Moore's law, has been continually opening up newer challenges to circuit designers. With rapid downscaling of integration, the intricacies involved in the manufacturing process have escalated significantly. Concomitantly, the nature of defects in silicon chips has become more complex and unpredictable, adding further difficulty in circuit testing and diagnosis. The volume of test data has surged and the parameters that govern testing of integrated circuits have increased not only in dimension but also in the complexity of their correlation. Evidently, the current scenario serves as a pertinent platform to explore new test solutions based on machine learning. In this survey, we look at various recent advances in this evolving domain in the context of digital logic testing and diagnosis.

Novel Ternary Adder and Multiplier Designs Without Using Decoders or Encoders

Abstract: Multiple-Valued Logic systems present significant improvements in terms of energy consumption over binary logic systems. This paper proposes new ternary combinational digital circuits that reduce energy consumption in low-power nano-scale embedded systems and Internet of Thing (IoT) devices to save their battery consumption. The 32 nm CNTFET-based ternary half adder (THA) and multiplier (TMUL) circuits use novel ternary unary operator circuits and implement two power supplies Vdd and Vdd/2 without using any ternary decoders, basic logic gates, or encoders to minimize the number of used transistors and improve the energy efficiency. Extensive simulations (over 160) of the proposed designs in terms of PVT (Process, Voltage, Temperature) variations, noise effect, and scalability studies, along with several benchmark designs using HSPICE simulator, prove the significance of the proposed circuits to decrease the power-delay product (PDP), improve the robustness to process variations, and the noise tolerance. The obtained results show the superiority of the designs in a reduction between 32% and 74% in transistors count and between 18% and 99% in PDP compared to the most recent works.

Novel Circuits Design for SISO Shift Register in QCA Technology

Abstract: The quantum-dot cellular automata technology has great attention in nanoscale digital circuits design due to its high-speed and high-dense. Shift registers play vital role in digital circuits desig...

Niobium Neuron: RSFQ Based Bio-Inspired Circuit

Abstract: Neuromorphic and bio-inspired circuits have reached considerable attention since Moore's Law is coming to its limitations. Information processing in mammalian brains takes place in a far more energy-efficient manner and significantly faster than in the best computing architecture nowadays. We propose an approach to bring those benefits to a superconducting information processing circuit. Since the computation in a neuronal network is considered as analogue and the computation as digital, the design is grown around a Josephson comparator with its inherent non-linearity in the transfer function as the central information processing unit. Furthermore, a modified version of the Josephson Transmission Line is used to realize an adaptable coupling between neuron cells. This circuit design benefits of the noise in a 4.2 K environment and is therefore more resilient to noise and switching errors than conventional digital circuits. The proposed circuit behavior in a 2-neuron configuration and the integration in a network topology will be investigated.

Ultra-Low-Power FDSOI Neural Circuits for Extreme-Edge Neuromorphic Intelligence

Abstract: Recent years have seen an increasing interest in the development of artificial intelligence circuits and systems for edge computing applications. In-memory computing mixed-signal neuromorphic architectures provide promising ultra-low-power solutions for edge-computing sensory-processing applications, thanks to their ability to emulate spiking neural networks in real-time. The fine-grain parallelism offered by this approach allows such neural circuits to process the sensory data efficiently by adapting their dynamics to the ones of the sensed signals, without having to resort to the time-multiplexed computing paradigm of von Neumann architectures. To reduce power consumption even further, we present a set of mixed-signal analog/digital circuits that exploit the features of advanced Fully-Depleted Silicon on Insulator (FDSOI) integration processes. Specifically, we explore the options of advanced FDSOI technologies to address analog design issues and optimize the design of the synapse integrator and of the adaptive neuron circuits accordingly. We present circuit post-layout simulation results and demonstrate the circuit’s ability to produce biologically plausible neural dynamics with compact designs, optimized for the realization of large-scale spiking neural networks in neuromorphic processors.

Photonic computing to accelerate data processing in wireless communications

Abstract: Massive multiple-input multiple-output (MIMO) systems are considered as one of the leading technologies employed in the next generations of wireless communication networks (5G), which promise to provide higher spectral efficiency, lower latency, and more reliability. Due to the massive number of devices served by the base stations (BS) equipped with large antenna arrays, massive-MIMO systems need to perform high-dimensional signal processing in a considerably short amount of time. The computational complexity of such data processing, while satisfying the energy and latency requirements, is beyond the capabilities of the conventional widely-used digital electronics-based computing, i.e., Field-Programmable Gate Arrays (FPGAs) and Application-Specific Integrated Circuits (ASICs). In this paper, the speed and lossless propagation of light is exploited to introduce a photonic computing approach that addresses the high computational complexity required by massive-MIMO systems. The proposed computing approach is based on photonic implementation of multiply and accumulate (MAC) operation achieved by broadcast-and-weight (B&W) architecture. The B&W protocol is limited to real and positive values to perform MAC operations. In this work, preprocessing steps are developed to enable the proposed photonic computing architecture to accept any arbitrary values as the input. This is a requirement for wireless communication systems that typically deal with complex values. Numerical analysis shows that the performance of the wireless communication system is not degraded by the proposed photonic computing architecture, while it provides significant improvements in time and energy efficiency for massive-MIMO systems as compared to the most powerful Graphics Processing Units (GPUs).

Superconducting Circuits without Inductors Based on Bistable Josephson Junctions

Abstract: Magnetic flux quantization in superconductors allows the implementation of fast and energy-efficient digital superconducting circuits. However, information representation in magnetic flux severely limits the functional density and is a long-standing problem. Here, we introduce the concept of superconducting digital circuits that do not utilize magnetic flux and have no inductors. We argue that neither the use of geometric nor kinetic inductance is promising for the scaling down of superconducting circuits. The key idea of our approach is the utilization of bistable Josephson junctions, allowing the representation of information through the Josephson energy. Since the proposed circuits are composed only of Josephson junctions, they can be called all-Josephson junction (all-JJ) circuits. We present a methodology for the design of circuits consisting of conventional and bistable junctions. We analyze the principles of the circuit's functioning, ranging from simple logic cells to an 8-bit parallel adder. The utilization of bistable junctions in the all-JJ circuits is promising for the simplification of schematics and a decrease of the JJ count, leading to space efficiency.

Design and simulation of efficient combinational circuits based on a new XOR structure in QCA technology

Abstract: Quantum-dot cellular automata (QCA), due to its unique characteristics like low power consumption, nanoscale design, and high computing speed is considered as an emerging technology, and it can be used as an alternative for CMOS technology in circuit design for quantum computers in the near future. XOR gate has many applications in the design of digital circuits in QCA. In this paper, an efficient novel structure of XOR gate is proposed in QCA. Also, a novel 1-bit comparator circuit, 1-bit full adder, binary to gray and gray to binary convertor code based on the proposed XOR is designed and simulated using QCADesigner 2.0.3. The simulation results demonstrated that the proposed structures provide improvements compared to previous works in terms of QCA cells count, area, and circuit cost.

A Novel Standard-Cell-Based Implementation of the Digital OTA Suitable for Automatic Place and Route

Abstract: This paper presents a novel implementation of a digital-based Operational Transconductance Amplifier (OTA) which has been recently introduced in the technical literature as a fully digital alternative to the conventional differential pair to implement low voltage analog amplifiers and comparators. The proposed implementation does not make use of resistors, floating gate resistors nor C-Muller elements and is made up of only digital gates usually available in the standard cell libraries. The resulting analog circuit schematic can be described using structural VHDL or Verilog languages and is suitable to be integrated in an automatic synthesis and place and route flow for digital circuits. The proposed digital-based amplifier has been implemented in a commercial 130 nm CMOS process by using an automatic place and route flow for layout generation starting from the Verilog netlist. Post layout simulations are presented to show the performance of the proposed circuit and compare it against the state of the art.

A Digital Signal Processing Based Detection Circuit for Short-Circuit Protection of SiC MOSFET

Abstract: A short-circuit detection (SCD) circuit is proposed for power electronics systems that use silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors ( MOSFET s). The proposed SCD circuit incorporates a digital circuit for processing the voltage induced at the parasitic inductance of the source of SiC MOSFET to obtain an improved stable turn- off operation of the SiC MOSFET under SC condition. Compared with that of the conventional analog signal processing based SCD circuits, the proposed circuit has the advantages of having a turn- off operation which is robust to process, voltage, and temperature variations, being fully integrated without the use of external components and ease of design. The proposed circuit was implemented in a 350-nm Bipolar-CMOS-DMOS process. For functional verification, an SC test board integrating the proposed SCD circuit was developed. Experimental result validates that the proposed SCD circuit effectively functions under SC condition.

Binary Coded Decimal (BCD) Seven Segment Circuit Designing using Quantum-dot Cellular Automata (QCA)

Abstract: QCA is an alternative nanotechnology which keeps scaling down the technology further. It can do scaling beyond to a level where complementary metal oxide semiconductor (CMOS) scaling rises the issue. QCA is seen as an emerging solution for nano-architectures. This nanotechnology uses different logic devices for digital circuit designing for obtaining a high rate of performance at output. This new nanotechnology uses a specific method to represent and decode the data. The main aim behind our work is to understand the basic QCA technology and to get familiar with the QCA designer 2.03 software for getting involved in advanced designing of digital circuits using QCA. In our work, Seven Segment Display is proposed using different gates and majority voters in QCA. A seven Segment Display uses Light Emitting Diodes to display output that can be in the form of image, text or decimal number. The simulation results verify that our work is significant.

Demonstration of a 47.8 GHz High-Speed FFT Processor Using Single-Flux-Quantum Technology

Abstract: A fast Fourier transform (FFT) is an algorithm that computes the discrete Fourier transform (DFT) of a sequence at high speed. FFT can convert a signal from time domain to frequency domain, and is wildly used in digital signal processing field. In this paper, a high-speed, low-power FFT processor is demonstrated up to 47.8GHz with the measured power consumption of 5.3mW, using single-flux quantum (SFQ) logic. This is the first complete FFT processor implementation using superconducting technology, performing 8-point 7-bit FFT in a bit-serial computing manner. The test chip fabricated using a 1.0 $\mu$ m 9-layer process consists of 17 455 Nb/AlOx/Nb Josephson junctions (JJs), rendering itself the largest superconducting digital circuit capable of iterative data computing. The correct operation of the chip has been experimentally confirmed at a maximum operating frequency of 47.8GHz (word speed 8GHz) by conducting on-chip high-speed testing.

Variation resilient low-power memristor-based synchronous flip-flops: design and analysis

Abstract: Flip-flops are the basic digital components for all types of complex digital electronics systems and sequential logic circuits. In this paper, new nonvolatile, low power, robust, compact and fully integrable SR and D flip-flops using a mathematical model of the memristor and CMOS are proposed. The memristor model captures all the well-established features of the memristor devices. A thorough investigation of the electrical response of memristor has been done and based on that the most suitable mechanisms for read and write operations have been recommended and their advantages are also listed. To propose a low power and reliable flip-flop, the nonvolatile nature of memristor is utilized. The tradeoffs between the design parameters such as read and write access times, energy dissipation and robustness have been analyzed. CMOS based transmission gates have been used to provide access for the inputs to the internal memristors of the architecture during write operations. The simulation is performed utilizing a 45-nm CMOS model.

25-GHz Operation of ERSFQ Time-to-Digital Converter

Abstract: Fast time-to-digital converters (TDCs), used to convert a continuous time interval into discrete number for further processing, serve diverse applications ranging from photon/particle detectors to communication systems employing delay-encoded pulses. Being a multi-rate digital circuit, the TDC is also a good candidate to explore operation of Energy-Efficient Rapid Single Flux Quantum (ERSFQ) circuits at high (>10 GHz) clock frequency. We designed a TDC using ERSFQ cells, targeting the 10-kA/cm2 SFQ5ee fabrication process at MIT Lincoln Laboratory. The main elements of the circuit comprise a 9-bit binary ripple counter and a parallel-to-serial converter. A frequency divider and a pulse distribution network with a decision-making element are designed to control the operation. The ERSFQ TDC was operated up to 25 GHz clock frequency (40 ps time resolution) and with a power consumption of around 14 µW for all ERSFQ components. The design specifications such as number of junctions and area will be discussed together with the power delivery technique involving an over-pumped feeding Josephson transmission line (JTL).

The Development of an Efficient 2-to-4 Decoder in Quantum-Dot Cellular Automata

Abstract: Quantum-dot cellular automata (QCA) is known as one of the best alternative technologies for CMOS on nano-scale dimensions, which allows the design of digital circuits with high speed and density. Decoders are considered as one of the most widely used combinational circuits. They also play an important role in designing circuits such as FPGA, CLB, and memory addressing. In this paper, we propose an effective design of the 2-to-4 decoder in the QCA technology. The proposed design consists of only three inverter gates and six 3-input majority gates. Two single-layer and three-layer of the proposed 2-to-4 QCA decoder with only 56 and 62 cells are provided and they require 3 and 4 clock cycles respectively. Also, one multi-layer 3-to-8 QCA decoder is developed and implemented using the proposed 2-to-4 QCA decoder. The proposed circuits are simulated using the QCADesigner 2.0.3 tool. A comparison of the proposed 2-to-4 QCA decoder with related designs shows that the proposed decoder has a good performance in terms of the number of cells, the occupied area, and the delay criteria. Also, the QCAPro tool is used to compute the power dissipation of the proposed decoder. Finally, the results are affirmed by physical proofs.

Inkjet-printed low-dimensional materials-based complementary electronic circuits on paper

Abstract: Complementary electronics has represented the corner stone of the digital era, and silicon technology has enabled this accomplishment. At the dawn of the flexible and wearable electronics age, the seek for new materials enabling the integration of complementary metal-oxide semiconductor (CMOS) technology on flexible substrates, finds in low-dimensional materials (either 1D or 2D) extraordinary candidates. Here, we show that the main building blocks for digital electronics can be obtained by exploiting 2D materials like molybdenum disulfide, hexagonal boron nitride and 1D materials such as carbon nanotubes through the inkjet-printing technique. In particular, we show that the proposed approach enables the fabrication of logic gates and a basic sequential network on a flexible substrate such as paper, with a performance already comparable with mainstream organic technology.

Low-power integrated circuits for wearable electrophysiology

Abstract: This chapter presents an overview of the fundamentals and state of the art in non-invasive biopotential recording instrumentation with a focus on micro-power integrated circuit design for high-density and unobtrusive wearable applications. Fundamental limits in sampling, noise, and energy efficiency in the design of front-end biopotential amplifiers and acquisition circuits are reviewed, and practical circuits that approach these limits using metal-oxide semi-conductor transistors operating in the subthreshold and weak-inversion regime are presented. Analog-to-digital converters (ADCs) for low-power applications are reviewed with a focus on successive-approximation-register ADC and ΔΣ ADC, along with some other alternative ADC architectures. Basic low-power design techniques for digital circuits and architectures are also reviewed with points of references. Examples are given of practical ultra-low-power circuits for biomedical wearable applications.