Digital electronics

About: Digital electronics is a research topic. Over the lifetime, 10354 publications have been published within this topic receiving 153532 citations.

Programmable Spin Logic Based on Spin Hall Effect in a Single Device

Abstract: Spin logic devices, due to their programmability and nonvolatility, are deemed as an ideal building block for the next generation of electronics. Though several types of spin logic based on domain wall motion, spin-field-effect transistor and automata made of magnetic nanoparticles have been proposed, an architecture with scalability, energy efficiency and compatibility with current complementary metal-oxide-semiconductor technology is still in urgent demand. Here, it is experimentally demonstrated that the spin Hall effect in magnetic films with perpendicular anisotropy can be utilized to construct such a spin logic device. Five commonly used logic gates with nonvolatility in a single device are realized. This demonstration could pave the way towards application of spintronics in logic circuits as well as the memory industry in the near future and could even give birth to logic-in-memory computing architectures.

Implementation of iterative networks with CMOS differential logic

Abstract: An improved differential CMOS logic family called enabled/disabled CMOS differential logic (ECDL) is presented. An extension to this logic technique which enables the implementation of iterative network arrays is also presented. Two simple logic functions, a Gray-to-binary decoder and an XOR cell, are implemented to demonstrate this methodology. >

Synthesis techniques for CMOS folded source-coupled logic circuits

Abstract: The application of series-gated, multiplexer-minimization, and variable-entered mapping methods to the synthesis of fully differential CMOS folded source-coupled logic (FSCL) gates is described. In contrast to conventional static logic, FSCL dissipates DC power. Its total power consumption is competitive at higher speeds where its low digital switching noise is most advantageous. The minimum propagation delay of a simple FSCL gate compares favorably to a conventional gate. Complex functions are generally faster in FSCL since its fully differential topology requires fewer stages of delay. Simulated and measured results are presented for several combinational and sequential FSCL gates in a 2- mu m p-well CMOS process. With V/sub dd/=5 V, a FSCL (static) inverter achieved a minimum propagation delay of 400 ps (350 ps) with a power-delay product of 0.5 pJ (0.3 pJ); a FSCL (static) 1-b full adder achieved a minimum delay of 3.0 ns (12.0 ns) with a power-delay product of 0.3 pJ (11.0 pJ). >