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Digital electronics

About: Digital electronics is a research topic. Over the lifetime, 10354 publications have been published within this topic receiving 153532 citations.


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Journal ArticleDOI
TL;DR: The proposed neuron-synapse integrated circuit (IC) chip-set makes it possible to construct a scalable and reconfigurable large-scale chaotic neural network with 10000 neurons and 10000/sup 2/ synaptic connections.
Abstract: We propose a neuron-synapse integrated circuit (IC) chip-set for large-scale chaotic neural networks. We use switched-capacitor (SC) circuit techniques to implement a three-internal-state transiently-chaotic neural network model. The SC chaotic neuron chip faithfully reproduces complex chaotic dynamics in real numbers through continuous state variables of the analog circuitry. We can digitally control most of the model parameters by means of programmable capacitive arrays embedded in the SC chaotic neuron chip. Since the output of the neuron is transfered into a digital pulse according to the all-or-nothing property of an axon, we design a synapse chip with digital circuits. We propose a memory-based synapse circuit architecture to achieve a rapid calculation of a vast number of weighted summations. Both of the SC neuron and the digital synapse circuits have been fabricated as IC forms. We have tested these IC chips extensively, and confirmed the functions and performance of the chip-set. The proposed neuron-synapse IC chip-set makes it possible to construct a scalable and reconfigurable large-scale chaotic neural network with 10000 neurons and 10000/sup 2/ synaptic connections.

61 citations

Journal ArticleDOI
TL;DR: It is shown that the logic hyperspace (product) vectors defined in the introductory paper can be generalized to provide the discrete superposition of 2 N orthogonal system states, equivalent to a multi-valued logic system with 2 2 N logic values per wire.

61 citations

Journal Article
TL;DR: Engineers have been proposing a new class of electronic devices that utilize quantum-mechanical principles (as opposed to classical principles) for their operation and these devices are often referred to as quantum devices or nanoelectronic devices since their physical dimensions are typically smaller than 100 nm.
Abstract: Engineers have been proposing a new class of electronic devices that utilize quantum-mechanical principles (as opposed to classical principles) for their operation. These devices are often referred to as quantum devices or nanoelectronic devices since their physical dimensions are typically smaller than 100 nm. The granularity of electric charge (namely that it can be found only in quanta of a single electron's charge) is a quantum-mechanical property. Similarly, the granularity of an electron's "spin" (namely that only certain polarizations may be allowed) is also a quantum-mechanical property. These two "granular" properties are quite robust; they, therefore, show much promise in actual device applications. Ultrafast and ultrasmall electronic devices that utilize the granularity of electric charge (and an associated effect known as Coulomb blockade) have been proposed for years. Boolean logic gates, combinational circuits and sequential memory have been designed with them. "Single electron transistors" (SET) built on this concept have been demonstrated experimentally. A newly proposed class of Boolean logic gates utilize a single electron as the primitive logic element (a bistable switch). Physical wires between devices are replaced by quantum-mechanical spin-spin couplings which communicate signals across the chip. These are unusual features which distinguish a "quantum circuit" from a conventional classical architecture.

61 citations

Proceedings ArticleDOI
18 Sep 1995
TL;DR: Simultaneous switching noise caused by parasitic inductance in the power supply distribution network is a severe problem in high speed digital circuits and systems and technical solutions for reducing SSN in the light of current developments of advanced packaging and assembly technologies are discussed.
Abstract: Simultaneous switching noise (SSN) caused by parasitic inductance in the power supply distribution network is a severe problem in high speed digital circuits and systems. The influence of SSN, negligible when rise/fall time is long (>5 ns), becomes an important factor, limiting circuit performance in the sub-nanosecond rise time region. This paper presents simulation results of SSN in high speed digital systems. Technical solutions for reducing SSN in the light of current developments of advanced packaging and assembly technologies are discussed. A quantitative comparison of SSN in digital systems implemented with conventional as well as advanced assembly techniques is given.

61 citations

Journal ArticleDOI
TL;DR: It is demonstrated that photovoltaic receivers, electrically driven transmitters and on-chip electronic circuits can all be fabricated using carbon nanotubes via a complementary metal oxide semiconductor-compatible low-temperature process, providing a seamless integration platform for realizing monolithic three-dimensional optoelectronic integrated circuits with diversified functionality such as the heterogeneous AND gates.
Abstract: Single material-based monolithic optoelectronic integration with complementary metal oxide semiconductor-compatible signal processing circuits is one of the most pursued approaches in the post-Moore era to realize rapid data communication and functional diversification in a limited three-dimensional space. Here, we report an electrically driven carbon nanotube-based on-chip three-dimensional optoelectronic integrated circuit. We demonstrate that photovoltaic receivers, electrically driven transmitters and on-chip electronic circuits can all be fabricated using carbon nanotubes via a complementary metal oxide semiconductor-compatible low-temperature process, providing a seamless integration platform for realizing monolithic three-dimensional optoelectronic integrated circuits with diversified functionality such as the heterogeneous AND gates. These circuits can be vertically scaled down to sub-30 nm and operates in photovoltaic mode at room temperature. Parallel optical communication between functional layers, for example, bottom-layer digital circuits and top-layer memory, has been demonstrated by mapping data using a 2 × 2 transmitter/receiver array, which could be extended as the next generation energy-efficient signal processing paradigm.

61 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202369
2022156
2021171
2020255
2019255
2018250