Digital electronics

About: Digital electronics is a research topic. Over the lifetime, 10354 publications have been published within this topic receiving 153532 citations.

Novel recharge semi-floating-gate CMOS logic for multiple-valued systems

Abstract: In this paper we present novel recharged logic for multiple-valued (MV) systems by utilizing semi-floating-gate (SFG) transistors. The recharged multiple-valued logic can be used to implement low-power digital circuits. The improvement in power dissipation is mainly in reduced dynamic power dissipation. The main purpose is to level out the power dissipated by a digital system to obtain more suitable logic for mixed mode design.

Band-to-Band Tunneling Ballistic Nanowire FET: Circuit-Compatible Device Modeling and Design of Ultra-Low-Power Digital Circuits and Memories

Abstract: Band-to-band tunneling (BTBT) nanowire FETs have been studied as a possible successor to CMOS FETs. In the literature, it has already been shown that a 1-D p+-i- n+-type semiconductor nanowire governed by a BTBT transport mechanism offers a subthreshold swing lower than the conventional limit of 60 mV/dec while maintaining a reasonable on-state performance. The concept of BTBT nanowire FETs is primitive, and the manufacturing process is nascent. In the absence of a suitable device model and/or a reliable circuit simulator, the evaluation and impact of such novel transistors are difficult to estimate. In this paper, we propose a simple complementary device model for BTBT nanowire FETs suitable for multitransistor circuit simulation and evaluate its performance in the ballistic limit. The device models so developed have been used to simulate a class digital logic circuits and dynamic memories (e.g., DRAM) to analyze their suitability in future very large scale integration design. Circuit level simulations explicitly show that the proposed p+ -i-n+-type BTBT nanowire FETs are well suited for medium throughput (approximately hundreds of kilohertz to a few tens of megahertz) ultra-low-power applications. The standby leakage power in memory and logic circuits has been found to be as low as 10-20 W due to the inherent super cutoff nature of the device. The presence of interconnect parasitics in parallel with intrinsic device capacitance severely limits the performance of digital circuits. The impact of interconnect parasitics on the performance of BTBT nanowire FETs has also been studied.

Dynamic logic CMOS circuits

Abstract: A structure of dynamic CMOS logic based on the direct interconnection of p-channel logic and n-channel logic dynamic gates is reported. Prevention of glitches and other circuit problems are discussed. Application to a 16-bit parallel-adder design resulted in improved speed as well as important savings in layout area when compared to standard static design.

Digital Anti-Windup PI Controllers for Variable-Speed Motor Drives Using FPGA and Stochastic Theory

Abstract: The windup phenomenon occurs when the output of a proportional-integral (PI) controller is saturated, which results in performance degradation or even instability. In this letter, three new anti-windup algorithms are proposed for a digital PI-speed controller to improve the control performance of variable-speed motor drives. These designs are implemented in a field programmable gate array (FPGA) device and stochastic theory is employed to enhance the computational capability of FPGA. Compared with conventional digital anti-windup techniques, the proposed methods offer several advantages: large dynamic range, easy digital design, minimal scaling of digital circuits, reconfigurability, and direct hardware implementation, while maintaining high control performance. The developed controllers are applied to the speed control of a field-oriented controlled induction motor drive using a hardware-in-the-loop test bench. The improved speed responses confirm the effectiveness of the proposed anti-windup schemes

CMOS multiple-valued logic design. I. Circuit implementation

Abstract: A CMOS circuit implementation of a functionally complete multiple-valued logic (MVL) set of operators is proposed. The set consists of literal, cycle, complement of literal, complement of cycle, min, and tsum operators. In all of the circuits, multiple-valued logic levels are represented in terms of current values. Binary voltage signals are generated inside the circuits using a threshold circuit element. These binary voltage signals are used to generate control signals for switches to realize appropriate current levels for the desired multiple-valued logic levels. Transient analysis simulations (using HSPICE) to verify the functionality of the designed circuits and the effect of variation in process parameters are also reported. >