Digital electronics

About: Digital electronics is a research topic. Over the lifetime, 10354 publications have been published within this topic receiving 153532 citations.

An LDPC Decoder With Time-Domain Analog and Digital Mixed-Signal Processing

Abstract: Time-domain analog and digital mixed-signal processing (TD-AMS) is presented. Analog computation is more energy- and area-efficient at the cost of its limited accuracy, whereas digital computation is more versatile and derives greater benefits from technology scaling. Besides, design automation tools for digital circuits are much more sophisticated than those for analog circuits. TD-AMS exploits both advantages, and is a solution better suited to implementing a system on chip including functions for which high computational accuracy is not required, such as error correction, image processing, and machine learning. As an example, a low-density parity-check (LDPC) code decoder with the technique is implemented in 65 nm CMOS and achieves the best reported efficiencies of 10.4 pJ/bit and 6.1 Gbps/mm2.

Sub-kBT micro-electromechanical irreversible logic gate.

Abstract: In modern computers, computation is performed by assembling together sets of logic gates. Popular gates like AND, OR and XOR, processing two logic inputs and yielding one logic output, are often addressed as irreversible logic gates, where the sole knowledge of the output logic value is not sufficient to infer the logic value of the two inputs. Such gates are usually believed to be bounded to dissipate a finite minimum amount of energy determined by the input-output information difference. Here we show that this is not necessarily the case, by presenting an experiment where a OR logic gate, realized with a micro-electromechanical cantilever, is operated with energy well below the expected limit, provided the operation is slow enough and frictional phenomena are properly addressed.

Efficient automatic diagnosis of digital circuits

Abstract: The problem of automatic diagnosis of digital circuits with efficiency is studied. Two improvements over the method of J.C. Madre et al. (1989) are developed to enhance the efficiency of diagnosis. Specifically, the dominance relation in circuit topology is utilized to reduce the search space of possibly correctable gates. In the authors' experiment, the search space is reduced to about one-half. A novel divide-and-conquer technique to determine the correct gate function is proposed. >

Fully Nonvolatile and Low Power Full Adder Based on Spin Transfer Torque Magnetic Tunnel Junction With Spin-Hall Effect Assistance

Abstract: As technology node scales down below 90 nm, the conventional complementary metal oxide semiconductor (CMOS) logic circuits suffer from various problems such as high standby power due to increase in leakage current. Spintronic devices based on magnetic tunnel junction (MTJ) is one of the most promising technology candidates for the future of the digital circuits. MTJ-based logic circuits can offer nonvolatility, high endurance, high density, low standby power dissipation, and 3-D integration capability with the CMOS technology. In recent years, several full-adder circuits are proposed based on MTJs that are not fully nonvolatile since they use MTJs to store only one of their inputs. This paper proposes a fully nonvolatile magnetic full-adder (MFA) circuit offering the capability of power gating with no loss of data. The proposed circuit stores all the inputs in MTJs using the spin-transfer torque (STT) method assisted by the spin-Hall effect (SHE). Thanks to the SHE assistance, delay and power consumption of the MTJ switching are reduced significantly. Moreover, as a result of lower write current, the endurance of the oxide barrier can be increased. Using a three-terminal SHE–STT–MTJ model and a 45 nm CMOS SPICE model, we simulated and validated the functionality of our design and compared it with some recent previous MFAs. Simulation results reveal that the proposed MFA offers considerable superiorities over the recent counterparts.

Systems Analysis of a TDM-FDM Translator/Digital A-Type Channel Bank

Abstract: In keeping with the trend to greater use of digital circuits for signal processing, a project was undertaken to realize in an exploratory way an important telecommunication function using as great a proportion of digital hardware as possible. The function chosen is that of the A -channel bank; viz., the frequency division multiplexing (FDM) of 12 voiceband signals onto a single wire. Because of the nature of its operation the device to be described can also perform a translation between FDM analog signals and time division multiplexed (TDM) digital signals. This paper describes the overall system design of the device with particular emphasis on a noise analysis. The principal sources of noise are the A/D conversion points and the roundoff points that occur at the outputs of multipliers. Each noise source is examined in turn and its contribution to the total noise assessed. It is concluded that the A/D conversion points are the most important noise sources and the most costly to deal with.