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Digital electronics
About: Digital electronics is a research topic. Over the lifetime, 10354 publications have been published within this topic receiving 153532 citations.
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13 Sep 2004
TL;DR: Logic and memory design techniques allowing subthreshold operation are developed and demonstrated and the fabricated 1024-point FFT processor operates down to 180mV using a standard 0.18/spl mu/m CMOS logic process while using 155nJ/FFT at the optimal operating point.
Abstract: Minimizing energy requires scaling supply voltages below device thresholds. Logic and memory design techniques allowing subthreshold operation are developed and demonstrated. The fabricated 1024-point FFT processor operates down to 180mV using a standard 0.18/spl mu/m CMOS logic process while using 155nJ/FFT at the optimal operating point.
270 citations
Book•
01 Jan 1983
TL;DR: In this article, a formalism called interval temporal logic (ITL) was proposed for describing the behavior of a wide variety of timing-dependent digital circuits, including delay elements, adders, latches, flip-flops, counters, random access memories, a clocked multiplication circuit and the Am2901 bit slice.
Abstract: : Predicate logic is a powerful and general descriptive formalism with a long history of development. However, since the logic's underlying semantics have no notion of time, statements such as I increases by 2 and The bit signal X rises from 0 to 1 can not be directly expressed. The author presents a formalism called interval temporal logic (ITL) that augments standard predicate logic with time-dependent operators. ITL is like discrete linear-time temporal logic but includes time intervals. The behavior of programs and hardware devices can often be decomposed into successively smaller intervals of activity. State transitions can be characterized by properties relating the initial and final values of variables over intervals. Furthermore, these time periods provide a convenient framework for introducing quantitative timing details. After giving some motivation for reasoning about hardware, he presents the propositional and first-order syntax and semantics of ITL. Demonstrated is ITL's utility for uniformly describing the structure and dynamics of a wide variety of timing-dependent digital circuits. Devices discussed include delay elements, adders, latches, flip-flops, counters, random-access memories, a clocked multiplication circuit and the Am2901 bit slice. ITL also provides a means for expressing properties of such specifications. Also examine are such concepts as device equivalence and internal states. Propositional ITL is shown to be undecidable although useful subsets are of relatively reasonable computational complexity. (Author)
265 citations
TL;DR: In this article, the performance of VCO-based ADCs in the presence of nonidealities such as jitter, nonlinearity, mismatch, and the metastability of D flip-flops is analyzed.
Abstract: A voltage-controlled oscillator (VCO) based analog-to-digital converter (ADC) is a time-based architecture with a first-order noise-shaping property, which can be implemented using a VCO and digital circuits. This paper analyzes the performance of VCO-based ADCs in the presence of nonidealities such as jitter, nonlinearity, mismatch, and the metastability of D flip-flops. Based on this analysis, design criteria for determining parameters for VCO-based ADCs are described. In addition, a digital calibration technique to enhance the spurious-free dynamic range degraded by the nonlinearity is also introduced. To verify the theoretical analysis, a prototype chip is implemented in a 0.13-?m CMOS process. With a 500-MHz sampling frequency, the prototype achieves a signal-to-noise ratio ranging from 71.8 to 21.3 dB for an input bandwidth of 100 kHz-247 MHz, while dissipating 12.6 mW and occupying an area of 0.078 mm2.
253 citations
25 Feb 1991
TL;DR: The authors present variable ordering methods of BDD based on cover patterns and selects most binate variables first, and the one for multi-level circuits is based on depth first traverse of circuits.
Abstract: We have developed multi-level logic minimization programs using Binary Decision Diagram (BDD). Here we present variable ordering methods of BDD. The variable ordering algorithm for two-level circuits is based on cover patterns and selects most binate variables first, and the one for multi-level circutis is based on depth first traverse of circuits. In both cases, the acquired variable orderings are optimized by exchanging a variable with its neighbor in the ordering.
249 citations
TL;DR: The delay modeler executes 10 000 times as fast as SPICE, yet produces delay estimates that are typically within 10 percent of SPICE for digital circuits.
Abstract: Crystal is a timing verification program for digital nMOS and CMOS circuits. Using the circuit extracted from a mask set, the program determines the length of each clock phase and pinpoints the longest paths. Crystal can process circuits with about 40 000 transistors in about 20-30 min of VAX-11/780 CPU time. The program uses a switch-level approach in which the circuit is decomposed into chains of switches called stages. A depth-first search, with pruning, is used to trace out stages and locate the critical paths. Bidirectional pass transistor arrays are handled by having the designer tag such structures with flow control information, which is used by Crystal to avoid endless searches. Delays are computed on a stage-by-stage basis, using a simple resistor-switch model based on rise-time ratios (a measure of how fully turned-on the transistors in the stage are). The delay modeler executes 10 000 times as fast as SPICE, yet produces delay estimates that are typically within 10 percent of SPICE for digital circuits.
246 citations