Digital electronics

About: Digital electronics is a research topic. Over the lifetime, 10354 publications have been published within this topic receiving 153532 citations.

ILLIADS: a fast timing and reliability simulator for digital MOS circuits

Abstract: The authors introduce ILLIADS as a fast MOS timing and reliability simulator for very large digital MOS circuits. The use of the proposed general circuit primitive not only provides better accuracy but also significantly reduces the simulation time. The use of an analytic solution embedded in the simulation engine improves both the simulation speed and the accuracy. Postponing the waveform approximation process provides better waveform approximation even for non-fully-switching waveforms and glitches. The channel length modulation effect is captured accurately in fast timing simulation with only 10% of speedup tradeoff. It is also shown that ILLIADS manifests the charge sharing problem. The modified PWCTC algorithm, PWCTC-W, which handles circuits with feedback, is introduced and shown to be superior to the dynamic-windowing scheme. It also does not manifest the window-growing problem and is insensitive to the level of strongly concerned component (SCC) hierarchy. The use of this algorithm keeps the speedup of ILLIADS over SPICE for circuits with feedbacks at the same level as that for combinational circuits. >

Characterization and parameterized generation of synthetic combinational benchmark circuits

Abstract: The development of new field-programmed, mask-programmed, and laser-programmed gate-array architectures is hampered by the lack of realistic test circuits that exercise both the architectures and their automatic placement and routing algorithms. In this paper, we present a method and a tool for generating parameterized and realistic synthetic circuits. To obtain the realism, we propose a set of graph-theoretic characteristics that describe a physical netlist, and have built a tool that can measure these characteristics on existing circuits. The generation tool uses the characteristics as constraints in the synthetic circuit generation. To validate the quality of the generated netlists, parameters that are not specified in the generation are compared with those of real circuits and with those of more "random" graphs.

On the design of robust multiple fault testable CMOS combinational logic circuits

Abstract: Tests that detect modeled faults independent of the delays in the circuit under test are called robust tests. An integrated approach to the design of combinational logic circuits in which all single stuck-open faults and path delay faults are detectable by robust tests was presented by the authors earlier. It is shown that the earlier design actually results in circuits in which all multiple stuck-at and stuck-open and multipath delay faults are robustly testable. The tests to detect such faults are presented. >

Performance comparison of analog and digital circuits

Abstract: It is the purpose of this paper to compare analog and digital semiconductor circuits. Using simple models, performance of these circuits will be evaluated as far as signal-to-noise ratio, power dissipation, bandwidth, and system capacity are concerned.