Digital electronics

About: Digital electronics is a research topic. Over the lifetime, 10354 publications have been published within this topic receiving 153532 citations.

Regularity and Symmetry as a Base for Efficient Realization of Reversible Logic Circuits

Abstract: We introduce a Reversible Programmable Gate Array (RPGA) based on regular structure to realize binary functions in reversible logic. This structure, called a 2 * 2 Net Structure, allows for more efficient realization of symmetric functions than the methods shown by previous authors. In addition, it realizes many non-symmetric functions even without variable repetition. Our synthesis method to RPGAs allows to realize arbitrary symmetric function in a completely regular structure of reversible gates with smaller “garbage” than the previously presented papers. Because every Boolean function is symmetrizable by repeating input variables, our method is applicable to arbitrary multi-input, multi-output Boolean functions and realizes such arbitrary function in a circuit with a relatively small number of garbage gate outputs. The method can be also used in classical logic. Its advantages in terms of numbers of gates and inputs/outputs are especially seen for symmetric or incompletely specified functions with many outputs.

Low-pass filter for computing the transition density in digital circuits

Abstract: Estimating the power dissipation and the reliability of integrated circuits is a major concern of the semiconductor industry. Previously, we showed that a good measure of power dissipation and reliability is the extent of circuit switching activity, called the transition density (see ibid., vol. 12, no. 2, p. 310-23, 1993). However, the algorithm for computing the density in the afore-mentioned paper is very basic and does not take into account the effect of inertial delays of logic gates. Thus, as we will show in this paper, the transition density may be severely overestimated in high-frequency applications. To overcome this problem, we model the effect of gate delay on logic signals in the form of a conceptual low-pass filter module that does not allow unacceptably short logic pulses to propagate. Using a stochastic model of logic signals, we then derive the equations required to propagate the transition density through the filter. We will present experimental results that illustrate the validity and importance of these results. >

Analysis of heterojunction bipolar transistor/resonant tunneling diode logic for low-power and high-speed digital applications

Abstract: A high-speed digital logic family based on heterojunction bipolar transistors (HBTs) and resonant tunneling diodes (RTDs) is proposed. The negative differential resistance of RTDs is used to significantly decrease the static power dissipation. SPICE simulations indicate that propagation delay time below 150 ps at 0.09-mW static power per gate should be obtainable. >

Reconfigurable Hybrid CMOS/Nanodevice Circuits for Image Processing

Abstract: We have analyzed two options of using hybrid CMOS/nanodevice circuits with area-distributed (CMOL) interface for the low-level image processing tasks, on the simplest example of 2-D image convolution with a sizable filter window. The first option is to use digital, DSP-like circuits based on a reconfigurable CMOL fabric, while the second one is based on mixed-signal CMOL circuits with the analog presentation of input and output data and the binary presentation of the filter function. Estimates of the circuit performance have been carried out for the 45-nm CMOS technology and the 4.5-nm nanowire half-pitch, and the power consumption fixed at a manageable, ITRS-specified level. In the digital case, the circuit area per pixel is about 25times25 , and the time necessary for convolving a 1024times1024-pixel, 12-bit-accurate image with a 3232-pixel window function of similar accuracy is close to 25 , much shorter than that estimated for purely CMOS circuits with the same minimum feature size on 45 nm. For a mixed-signal CMOL circuit, the corresponding numbers are much better ( ~1 mum2 and 1mus, respectively), but this option requires a very high (~1%) reproducibility of on currents of the necessary crosspoint devices (programmable diodes), which has not yet been reached experimentally.

Don't care set specifications in combinational and synchronous logic circuits

Abstract: A unified framework for the specification and computation of don't care conditions for combinational and synchronous multiple-level digital circuits is presented. Circuits are characterized in terms of graphs, logic functions and don't care conditions induced by the external and internal interconnections. The replacement of a gate in a synchronous logic network is modeled by a perturbation of the corresponding logic function, and it is shown that the don't care conditions for the gate optimization represent the bound on this perturbation. Algorithms to compute such don't care conditions in both the combinational and synchronous case are presented. The implementation of the algorithms and the experimental results are discussed. >