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Digital electronics

About: Digital electronics is a research topic. Over the lifetime, 10354 publications have been published within this topic receiving 153532 citations.


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Patent
23 Nov 1994
TL;DR: In this paper, a base station modulator for the digital cellular mobile communication system achieves reduced hardware complexity in a base band QPSK modulating circuit by applying the Multilevel Logic Operation (MLO) which is extended from the conventional binary exclusive-OR operation, to the conventional base station Modulator (BSM).
Abstract: A base station modulator for the digital cellular mobile communication system achieves reduced hardware complexity in a base band QPSK modulating circuit by applying the Multilevel Logic Operation (MLO) which is extended from the conventional binary exclusive-OR operation, to the conventional Base Station Modulator (BSM). The base station modulator includes a plurality of spreaders 621 for QPSK spreading of a voice data stream. These spreaders 621 employ binary-multilevel Logic (MLO) gates instead of multiple binary exclusive-OR gates. The binary-multilevel Logic gate includes a subtractor 510 and a selector 520. The subtractor has one input (-) to which multilevel logic values are applied and one input (+) to which a maximum logic level of the multilevel logic values is applied. The selector has one input to which the multilevel logic values are applied, one input to which the output signal of the subtractor 510 is applied, and one control input to which the binary logic value is applied. If the binary logic value is zero (0), the selector 520 selects and outputs the multilevel logic values, and if the binary logic value is one (1), the selector 520 selects and outputs the output signal from the subtractor 510.

51 citations

Proceedings ArticleDOI
10 Oct 1994
TL;DR: In this paper, a novel signature analysis scheme for analog and mixed-signal circuits is proposed and it is shown that if the input analog signal is imprecise within certain bounds, then the generated signature is also imprecising within certain limits.
Abstract: While the design of signature analyzers for digital circuits has been well researched in the past, signature analyzers for analog signals are relatively unknown. In this paper, a novel signature analysis scheme for analog and mixed-signal circuits is proposed. The signatures possess the interesting properly that if the input analog signal is imprecise within certain bounds (an inherent property of analog signals), then the generated signature is also imprecise within certain bounds. A failure is indicated by the generated signature being different from the expected signature by a margin greater than a predetermined threshold. >

51 citations

Book
01 Jan 1984
TL;DR: This is a modern revision of the classic digital design textbook that teaches the basic tools for the design of digital circuits in a clear, easily accessible manner and is accompanied by Verilog simulator software>SynaptiCAD's VeriLogger Pro evaluation version.
Abstract: From the Publisher: This is a modern revision of the classic digital design textbook. The book teaches the basic tools for the design of digital circuits in a clear, easily accessible manner. New to This Edition: Nine sections on Verilog Hardware Description Language (HDL) inserted in discrete sections, allowing the material to be covered or skipped as desired. The Verilog HDL presentation is at a suitable level for beginning students who are learning digital circuits for the first time. Reorganized material on combinational circuits is now covered in a single chapter. The emphasis in the sequential circuits chapters is now on design with D flip-flops instead of JK and SR flip-flops. The material on memory and programmable logic is now consolidated in one chapter. Chapter 8 consists mostly of new material and now covers digital design in the Register Transfer Level (RTL), preparing the reader for more advanced design projects and further Verilog HDL studies. A new section in Chapter 11 supplements the laboratory experiments with HDL experiments. These enable the reader to check the circuits designed in the laboratory by means of hardware components and/or by HDL simulation. Text accompanied by Verilog simulator software>SynaptiCAD's VeriLogger Pro evaluation version, a Verilog simulation environment that combines all of the features of a traditional Verilog simulator with a powerful graphical test vector generator. Fast model testing in VeriLogger Pro allows the reader to perform bottom-up testing of every model in a design. All of the HDL examples in thebook can be found on the CD-ROM. A Companion Website includes resources for instructors and students such as transparency masters of all figures in the book, all HDL code examples from the book, a Verilog tutorial, tutorials on using the VeriLogger Pro software, and more. CONTENTS Binary Systems Boolean Algebra and Logic Gates Gate-Level Minimization Combinational Logic Synchronous Sequential Logic Registers and Counters Memory and Programmable Logic Register Transfer Level Asynchronous Sequential Logic Digital Integrated Circuits Laboratory Experiments Standard Graphic Symbols

50 citations

Journal ArticleDOI
TL;DR: This work presents design schemes for a self-stabilizing microprocessor and a new technique for analyzing the effect of soft errors and shows that the problem of computing the reliability of a circuit such that logical masking is taken into account is an NP-hard problem.
Abstract: Soft errors are changes in memory value caused by external radiation or electrical noise. Decreases in computing feature sizes and power usages and shorting the microcycle period enhance the influence of soft errors. Self-stabilizing systems are designed to be started in an arbitrary, possibly a corrupted, state due to, say, soft errors, and to converge to a desired behavior. Self-stabilization is defined by the state space of the components and is essentially a well-founded, clearly defined form of the terms self-healing, automatic-recovery, automatic-repair, and autonomic-computing. To implement a self-stabilizing system, one needs to ensure that the microprocessor that executes the program is self-stabilizing. A self-stabilizing microprocessor copes with any combination of soft errors, converging to perform fetch-decode-execute in fault-free periods. Still, it is important that the microprocessor will avoid convergence periods if possible by masking the effect of soft errors immediately. In this work, we present design schemes for a self-stabilizing microprocessor and a new technique for analyzing the effect of soft errors. Previous schemes for analyzing the effect of soft errors were based on simulations. In contrast, our scheme computes a lower bound on microprocessor reliability and enables the microprocessor designer to evaluate the reliability of the design and to identify reliability bottlenecks. When analyzing the resiliency of digital circuits to soft errors, we examine the logical masking, i.e., errors in internal nodes of the circuits that are masked later by the computation. We show that the problem of computing the reliability of a circuit such that logical masking is taken into account is an NP-hard problem.

50 citations

Proceedings ArticleDOI
13 May 2002
TL;DR: A key aspect of the cooperative analog/digital signal processing systems is the fact that new advances in analog VLSI circuits make it possible to developed advanced analog signalprocessing systems with programmable elements.
Abstract: We introduce the concept of cooperative analog-digital signal processing, and its implications on real-time signal processing functions We discuss some of the trade-offs between performing operations in the analog computing circuit and digital computing circuits, and a general framework for “cooperative analog/digital signal processing systems” is presented A key aspect of the cooperative analog/digital signal processing systems is the fact that new advances in analog VLSI circuits make it possible to developed advanced analog signal processing systems with programmable elements

50 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202369
2022156
2021171
2020255
2019255
2018250