Digital electronics

About: Digital electronics is a research topic. Over the lifetime, 10354 publications have been published within this topic receiving 153532 citations.

Slope propagation in static timing analysis

Abstract: Static timing analysis has traditionally used the PERT method for identifying the critical path of a circuit. The authors show in this paper that due to the influence of the transition time of a signal on the subsequent path delay, the traditional timing analysis approach can report an optimistic circuit delay and may identify the wrong critical path. Also, the calculated circuit delay is a discontinuous function with respect to transistor and gate sizes, posing a severe problem for circuit optimization methods. The authors also examine an alternate approach where the propagated signal is constructed by combining the latest arrival time and the slowest transition time from all signals incident on a node. While this approach remedies the problem of discontinuity, it can significantly overestimate the circuit delay and can also identify the wrong critical path. In this paper, they therefore propose a new timing analysis algorithm and prove that it computes the correct and continuous timing graph delay and the proper critical path. The proposed algorithm selectively propagates multiple signals through each timing edge in cases where there exists ambiguity regarding which arriving signal represents the critical path. They show that the algorithm propagates the sufficient and necessary set of signals for computing the delay of a general timing graph. The authors also introduce a new property of digital gates, referred to as the transition shift property, and, using this property, show that the number of propagated signals can be significantly reduced for timing graphs of digital circuits. Finally, they discuss the computation of required times and node slacks for the traditional approaches and propose corresponding algorithms for the new approaches. They show that while the traditional approach can incur both a positive or negative error in the computed slack, the proposed algorithms compute a conservative slack for off-critical nodes and the correct and continuous slack for the critical path. The proposed algorithms were implemented in an industrial static timing analysis and optimization tool, and the authors present results for a number of industrial circuits. Their results show that the traditional timing analysis method underestimates the circuit delay by as much as 39%, while the discussed alternate approach can overestimate circuit delay by as much as 17%. The proposed method computes the correct delay, while incurring only a small run time overhead in all cases.

Fast timing simulation of transient faults in digital circuits

Abstract: Transient fault simulation is an important verification activity for circuits used in critical applications since such faults account for over 80% of all system failures. This paper presents a timing level transient fault simulator that bridges the gap between electrical and gate-level transient fault simulators. A generic MOS circuit primitive and analytical solutions of node differential equations are used to perform transistor level simulation with accurate MOS-FET models. The transient fault is modeled by a piecewise quadratic injected current waveform; this retains the electrical nature of the transient fault and provides SPICE-like accuracy. Detailed comparisons with SPICE3 show the accuracy of this technique and speedups of two orders of magnitude are observed for circuits containing up to 2000 transistors. Latched error distributions of the benchmark circuits are also provided.

Analysis and modeling of multilevel parallel and crossing interconnection lines

Abstract: Analytical and numerical techniques to study the pulse propagation characteristics such as delay, distortion, and crosstalk in multilevel interconnections associated with high-speed digital IC's including VLSI chips are presented. The parallel and crossing interconnections at various levels are modeled as lossy coupled lumped distributed parameter systems, which are analyzed for their time domain characteristics. The characterizing electrical parameters of the structures are computed by utilizing the network analog method that has been formulated to solve for the lossy line constants and parasitic coupling associated with a three-dimensional multiconductor system in a layered lossy medium. It is shown that the time domain response of the multiport structures can be computed by using standard CAD programs such as SPICE by utilizing compatible circuit models developed from the solution of such systems. Examples of the step and pulse response of typical systems are included to demonstrate the versatility, usefulness, and accuracy of the techniques presented in the paper.

Electronic circuits : design and applications

Abstract: This text on electronic circuit design and application, has been given a new title as it has been updated and widened in scope. Written both for the student and the practising engineer and scientist, the book covers major aspects and applications of modern analogue and digital circuit design. Part I concentrates on analogue and digital circuits, on operational amplifiers, combinatorial and sequential logic and memories. Part II is application-oriented. Each chapter offers various solutions to a given problem, and is designed to enable the reader to understand ready-made circuits and/or to proceed reasonably quickly from theory to a working circuit. The design approach is often illustrated by an example. Analogue applications cover such topics as analogue computing circuits. The digital sections deal with AD and DA conversion, digitial computing circuits, microprocessors and digital filters.