Topic
Digital electronics
About: Digital electronics is a research topic. Over the lifetime, 10354 publications have been published within this topic receiving 153532 citations.
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TL;DR: In this paper, the analog and digital circuits implemented in a dual threshold voltage p-channel organic technology are presented, which is compatible with large area and mechanically flexible substrates due to its low processing temperature (≤ 95°C) and scalable patterning techniques.
Abstract: Analog & digital circuits implemented in a dual threshold voltage (VT) p-channel organic technology are presented. The dual VT organic technology is compatible with large-area and mechanically flexible substrates due to its low processing temperature (≤ 95°C) and scalable patterning techniques. We demonstrate the first analog & digital organic integrated circuits produced by a dual-gate metal process. The analog circuits are powered by a 5-V supply and include a differential amplifier and a two-stage uncompensated operational amplifier (op-amp). A dynamic comparator is measured to have an input offset voltage of 200 mV and latching time of 119 ms. Both the comparator and the op-amp dissipate 5 nW or less. Area-minimized digital logic is presented. Inverters powered by a 3-V supply were measured to have positive noise margins and consumed picowatts of power. An 11-stage ring oscillator, also powered by a 3-V supply, swings near rail to rail at 1.7 Hz. These results demonstrate dual threshold voltage process feasibility for large-area flexible mixed-signal organic integrated circuits.
49 citations
06 Jun 1994
TL;DR: The EXMalgorithm, which locates multiple logic design errors in a combinational circuit with multiple output using an error possibility index and a six-valued simulation method, is presented.
Abstract: This paper presents the EXMalgorithm, which locates multiple logic design errors in a combinational circuit with multiple output. An error possibility index and a six-valued simulation method have been introduced to reduce the number of error candidates without missing real errors. Experimental results have shown that this algorithm locates all errors at high hit ratio for benchmark circuits.
49 citations
22 Aug 2001
TL;DR: This work expresses the classification rules as Boolean logic equations, build binary decision diagrams for these equations, and then map the BDDs to a logic network consisting of a pipeline of static RAM banks that generalizes to classifying packets on multiple fields.
Abstract: We present a solution to the problem of quickly classifying packets. Our approach is based on techniques from logic synthesis. Specifically, we express the classification rules as Boolean logic equations, build binary decision diagrams for these equations, and then map the BDDs to a logic network consisting of a pipeline of static RAM banks. We illustrate our approach by applying it to the longest prefix matching for IP forwarding, and present evidence that our scheme can perform a billion matches per second on a CAIDA backbone forwarding table containing 60,000 prefixes. We show how our approach generalizes to classifying packets on multiple fields.
49 citations
23 Sep 2011
TL;DR: The output of the digital circuit is proved to be chaotic by calculating the output time series maximum Lyapunov exponent and a new post processing technique is introduced to improve the distribution and statistical properties of the generated data.
Abstract: In this paper, we present a fully digital differential chaos based random number generator. The output of the digital circuit is proved to be chaotic by calculating the output time series maximum Lyapunov exponent. We introduce a new post processing technique to improve the distribution and statistical properties of the generated data. The post-processed output passes the NIST Sp. 800-22 statistical tests. The system is written in Verilog VHDL and realized on Xilinx Virtex® FPGA. The generator can fit into a very small area and have a maximum throughput of 2.1 Gb/s.
49 citations
TL;DR: This paper proposes an easy-to-develop and flexible FPGA-based fault injection technique that utilizes debugging facilities of Altera FPGAs in order to inject single event upset and multiple bit upset fault models in both flip-flops and memory units.
49 citations