Digital electronics

About: Digital electronics is a research topic. Over the lifetime, 10354 publications have been published within this topic receiving 153532 citations.

Design of robustly testable combinational logic circuits

Abstract: An integrated approach to the design of combinational logic circuits in which all path delay faults and multiple line stuck-at, transistor stuck-open faults are detectable by robust tests is proposed. Robustly testable static CMOS primitive logic circuit designs are presented for any arbitrary combinational logic function. They require no special gates, and fan-in and fan-out constraints do not affect the designs. Extra controllable inputs or additional hardware to achieve testability was not used. It is demonstrated that the method guarantees the design of CMOS logic circuits in which all path delay faults are locatable. >

Automatic Design for Testability Via Testability Measures

Abstract: In this paper we present a technique for the automatic design for testability of digital circuits based upon the analysis of controllability and observability measures. The new concept of sensitivity is introduced, which is a measure for the degree to which the testability of a circuit improves as increased controllability and observability is achieved over a set of nodes in a circuit. In order to improve the testability of a circuit, three simple transformations are used, namely, the addition of a new primary input and possibly an AND (OR) gate so that a logic 0(1) can be injected into the interior of the circuit, and test points so that internal signal values can be observed. We then introduce the global r-modification problem, which deals with making r (integer) transformations to a circuit in order to improve its testability. This resynthesis problem has been formulated as a mixed integer linear programming problem. A program called Testability Improvement Program (TIP) has been developed for implementing this approach, and experimental results are presented. The work presented is applicable to problems of test generation, the design of fixtures for ATE, and determining the location of test pads on integrated circuit chips when employing electron beam testing.

A novel CMOS implementation of double-edge-triggered flip-flops

Abstract: A CMOS implementation of a D-type double-edge-triggered flip-flop (DET-FF) is presented. A DET-FF changes its state at both the positive and the negative clock edge transitions. It has advantages with respect to both system speed and power dissipation. The design presented requires little overhead in circuit complexity. This CMOS D-type DET-FF is capable of operating at more than 50 MHz, which gives an equivalent system frequency of 100 MHz. >

Sample-set differential logic (SSDL) for complex high-speed VLSI

Abstract: An improved CMOS logic circuitusing a differential cascode tree with sample and set phases of operation is presented. The sample-set differential logic (SSDL) circuit allows the use of several transistors in series in the cascode tree without significant speed degradation. Also, the signals arriving at the input require only a short valid time, which allows long interconnect delays. This improved logic circuits is compared with two other common CMOS logic circuits in a simulated design example.

On-Chip Measurement of Deep Metastability in Synchronizers

Abstract: A deep metastability measurement scheme has been implemented on chip using digital circuits with 0.18 mum technology. Compared with previous off-chip implementations using analog circuits, the on-chip implementation allows integration of both the synchronizer circuits and the measurement method, and eliminates high-speed off-chip paths which are a source of inaccuracy. It also makes control at the picosecond level easier because of the inherent stability of digital integrating counters and digital delay lines. Our results show that the digital delay line used to adjust the data to clock times is controllable to an increment of 0.1 ps, and the input time distribution is 5.2 ps compared with 7.6 ps for the analog version. Because of the use of high and low counters, we can control the ratio of high to low outputs so that the actual input distribution can be measured to within better than 1 ps. The metastability time constant tau has been measured down to 10-17 s which corresponds to an mean time between failures (MTBF) of 100 seconds in an experimental time of 10 minutes and can be extended to a lower level by increasing the measurement time. Our results also show that a new synchronizer circuit designed for robustness to variation in Vdd performed at least as well as the Jamb Latch at all values of Vdd, and is more than 20% faster when Vdd was reduced by 25%.