Digital electronics

About: Digital electronics is a research topic. Over the lifetime, 10354 publications have been published within this topic receiving 153532 citations.

Evolvable systems : from biology to hardware : 7th International Conference, ICES 2007, Wuhan, China, September 21-23, 2007 : proceedings

Abstract: Digital Hardware Evolution.- An Online EHW Pattern Recognition System Applied to Sonar Spectrum Classification.- Design of Electronic Circuits Using a Divide-and-Conquer Approach.- Implementing Multi-VRC Cores to Evolve Combinational Logic Circuits in Parallel.- An Intrinsic Evolvable Hardware Based on Multiplexer Module Array.- Estimating Array Connectivity and Applying Multi-output Node Structure in Evolutionary Design of Digital Circuits.- Research on the Online Evaluation Approach for the Digital Evolvable Hardware.- Research on Multi-objective On-Line Evolution Technology of Digital Circuit Based on FPGA Model.- Evolutionary Design of Generic Combinational Multipliers Using Development.- Analog Hardware Evolution.- Automatic Synthesis of Practical Passive Filters Using Clonal Selection Principle-Based Gene Expression Programming.- Research on Fault-Tolerance of Analog Circuits Based on Evolvable Hardware.- Analog Circuit Evolution Based on FPTA-2.- Bio-inspired Systems.- Knowledge Network Management System with Medicine Self Repairing Strategy.- Design of a Cell in Embryonic Systems with Improved Efficiency and Fault-Tolerance.- Design on Operator-Based Reconfigurable Hardware Architecture and Cell Circuit.- Bio-inspired Systems with Self-developing Mechanisms.- Development of a Tiny Computer-Assisted Wireless EEG Biofeedback System.- Steps Forward to Evolve Bio-inspired Embryonic Cell-Based Electronic Systems.- Evolution of Polymorphic Self-checking Circuits.- Mechanical Hardware Evolution.- Sliding Algorithm for Reconfigurable Arrays of Processors.- System-Level Modeling and Multi-objective Evolutionary Design of Pipelined FFT Processors for Wireless OFDM Receivers.- Reducing the Area on a Chip Using a Bank of Evolved Filters.- Evolutionary Design.- Walsh Function Systems: The Bisectional Evolutional Generation Pattern.- Extrinsic Evolvable Hardware on the RISA Architecture.- Evolving and Analysing "Useful" Redundant Logic.- Adaptive Transmission Technique in Underwater Acoustic Wireless Communication.- Autonomous Robot Path Planning Based on Swarm Intelligence and Stream Functions.- Research on Adaptive System of the BTT-45 Air-to-Air Missile Based on Multilevel Hierarchical Intelligent Controller.- The Design of an Evolvable On-Board Computer.- Evolutionary Algorithms in Hardware Design.- Extending Artificial Development: Exploiting Environmental Information for the Achievement of Phenotypic Plasticity.- UDT-Based Multi-objective Evolutionary Design of Passive Power Filters of a Hybrid Power Filter System.- Designing Electronic Circuits by Means of Gene Expression Programming II.- Designing Polymorphic Circuits with Evolutionary Algorithm Based on Weighted Sum Method.- Robust and Efficient Multi-objective Automatic Adjustment for Optical Axes in Laser Systems Using Stochastic Binary Search Algorithm.- Minimization of the Redundant Sensor Nodes in Dense Wireless Sensor Networks.- Evolving in Extended Hamming Distance Space: Hierarchical Mutation Strategy and Local Learning Principle for EHW.- Hardware Implementation of Evolutionary Algorithms.- Adaptive and Evolvable Analog Electronics for Space Applications.- Improving Flexibility in On-Line Evolvable Systems by Reconfigurable Computing.- Evolutionary Design of Resilient Substitution Boxes: From Coding to Hardware Implementation.- A Sophisticated Architecture for Evolutionary Multiobjective Optimization Utilizing High Performance DSP.- FPGA-Based Genetic Algorithm Kernel Design.- Using Systolic Technique to Accelerate an EHW Engine for Lossless Image Compression.

Signal Integrity Design for High-Speed Digital Circuits: Progress and Directions

Abstract: This paper reviews recent progress and future directions of signal integrity design for high-speed digital circuits, focusing on four areas: signal propagation on transmission lines, discontinuity modeling and characterization, measurement techniques, and link-path design and analysis.

Digital Design and Computer Architecture

Abstract: "Digital Design and Computer Architecture" takes a unique and modern approach to digital design. Beginning with digital logic gates and progressing to the design of combinational and sequential circuits, Harris and Harris use these fundamental building blocks as the basis for what follows: the design of an actual MIPS processor. SystemVerilog and VHDL are integrated throughout the text in examples illustrating the methods and techniques for CAD-based circuit design. By the end of this book, readers will be able to build their own microprocessor and will have a top-to-bottom understanding of how it works. Harris and Harris have combined an engaging and humorous writing style with an updated and hands-on approach to digital design. This second edition has been updated with new content on I/O systems in the context of general purpose processors found in a PC as well as microcontrollers found almost everywhere. The new edition provides practical examples of how to interface with peripherals using RS232, SPI, motor control, interrupts, wireless, and analog-to-digital conversion. High-level descriptions of I/O interfaces found in PCs include USB, SDRAM, WiFi, PCI Express, and others. In addition to expanded and updated material throughout, SystemVerilog is now featured in the programming and code examples (replacing Verilog), alongside VHDL. This new edition also provides additional exercises and a new appendix on C programming to strengthen the connection between programming and processor architecture. It covers the fundamentals of digital logic design and reinforces logic concepts through the design of a MIPS microprocessor. It features side-by-side examples of the two most prominent Hardware Description Languages (HDLs)-SystemVerilog and VHDL - which illustrate and compare the ways each can be used in the design of digital systems. It includes examples throughout the text that enhance the reader's understanding and retention of key concepts and techniques. Companion Web site includes links to CAD tools for FPGA design from Altera and Mentor Graphics, lecture slides, laboratory projects, and solutions to exercises. Updated based on instructor feedback with more exercises and new examples of parallel and advanced architectures, practical I/O applications, embedded systems, and heterogeneous computing. It presents digital system design examples in both VHDL and SystemVerilog (updated for the second edition from Verilog), shown side-by-side to compare and contrast their strengths. It includes a new chapter on C programming to provide necessary prerequisites and strengthen the connection between programming and processor architecture. Instructors can also register at textbooks.elsevier.com for access to: solutions to all exercises (PDF); lab materials with solutions; HDL for textbook examples and exercise solutions; Lecture slides (PPT); Sample exams\ Sample course syllabus; and figures from the text (JPG, PPT).

Optical logic array processor using shadowgrams

Abstract: On the basis of a lensless shadow-casting technique, a new, simple method of optically implementing digital logic gates has been developed. These gates are capable of performing a complete set of logical operations on a large array of binary variables in parallel, i.e., the pattern logics. A light-emitting diode (LED) array is used as an incoherent light source in the lensless shadow-casting system. Sixteen possible functions of two binary variables are simply realizable with these gates in parallel by controlling the switching modes of the LED’s. Experimental results demonstrate the feasibility of various gate arrays, such as AND, OR, NOR, XOR, and NAND. As an example of application of the proposed method, we construct an optical logic array processor that can implement parallel operations of addition or subtraction for two binary variables without considering the carry mechanism. Use of the light-modulated LED array means that the proposed method can be applied to combinational circuits.

Single‐electron transistor logic

Abstract: We present the results of numerical simulations of a functionally complete set of complementary logic circuits based on capacitively coupled single‐electron transistors (CSETs). The family includes an inverter/buffer stage, as well as two‐input NOR, NAND, and XOR gates, all using similar tunnel junctions, and the same dc bias voltage and logic levels. Maximum operation temperature, switching speed, power consumption, noise tolerances, error rate, and critical parameter margins of the basic gates have been estimated. When combined with the data from a preliminary geometrical analysis, the results indicate that implementation of the CSET logic family for operation at T∼20 K will require fabrication of structures with ∼2‐nm‐wide islands separated by ∼1‐nm‐wide tunnel gaps.