Digital electronics

About: Digital electronics is a research topic. Over the lifetime, 10354 publications have been published within this topic receiving 153532 citations.

Soft-error filtering: A solution to the reliability problem of future VLSI digital circuits

Abstract: As the semiconductor industry continues to scale down the feature sizes in VLSI digital circuits, soft errors will eventually limit the reliability of these circuits. An important source of these errors will be the products of radioactive decay. It is proposed to combat these transient errors by a new technique called soft-error filtering (SEF). This is based on filtering the input to every latch in the VLSI circuit, thereby preventing these transients, generated by alpha particle hits in the combinational section, from being latched in the corresponding registers. Several approaches to the problem of designing filtering latches are compared. This comparison demonstrates the superiority of a double-filter realization. The design for a CMOS implementation of the double-filter latch is presented. Not only is the design simple and efficient, but it can be expected to be tolerant to process variations. A comparison of SEF with conventional techniques for dealing with soft errors shows the former to be generally much more attractive, from the point of view of both area and time overhead.

The dynamic load balancing of clustered time warp for logic simulation

Abstract: We present, in this paper, a dynamic load balancing aJ.gorit.hm developed for Clustered Time Warp, a hybrid approach which makes we of Time Warp bet.wwn clusters of LPs and a sequent.isl mechanism within the clusters. The load balancing algorithm focuses on distributing the load of the sirnnlat.ion evenly among the processors and then tries to reduce interprocesmr communicatiorw We make nse of a triggering techniqne based on the thronghpnt of the sinmlat.ion system. The algorithm was implemented and its performance W-M rneasnred usin two of the largest 8 benchmark digital circnits of the I CAS’89 series. In order t,o measnre the effects of the algorithm on worklm.d distribution, inter-proces..or communication and rollbacks, we defined three dktinct met rim. Results show that by dynamicaJ1y balancing the load, the throughput was improved by 40 to 100% when compared to Time Warp. Thrcmghpnt. is the nnmbw of non rolled-back message events per unit time. It’hen the algorithm tried to reduce inter-processor communication, rollbacks were substantially rwlnced. Nevertheless, no substantial improvement was observed on the overall simulation time, sng Ming that f load distribution is the most important actor to be taken into consideration in speeding up the simulation of d@jt.ai circuits.

A unified approach to the synthesis of fully testable sequential machines

Abstract: An attempt is made to unify and extend the various approaches to synthesizing fully testable sequential circuits that can be modeled as finite state machines (FSMs). The authors first identify classes of redundancies and isolate equivalent-state redundancies as those most difficult to eliminate. It is then shown that the essential problem behind equivalent-state redundancies is the creation of valid/invalid state pairs. The remainder of this research is devoted to techniques for developing differentiating sequences for valid/invalid state pairs created by a fault, as well as to techniques for retaining these sequences in the presence of that fault. A variety of techniques have been proposed to address this problem. At one end of the spectrum there are optimal synthesis procedures that ensure full testability by eliminating redundancies via the use of appropriate don't care sets. At the other end of the spectrum there are constrained synthesis procedures that produce fully and easily testable sequential circuits by restricting the implementation of the logic. The notion of fault-effect disjointness is used to explore the landscape between these two extremes and a spectrum of methods that place relatively more-or-less emphasis on either logic optimization or constrained synthesis is demonstrated. Techniques used in this exploration include fault simulation, Boolean covering, algebraic factorization, and state assignment. Experimental results using the proposed synthesis procedures and comparisons to previous approaches are presented. >

Scannable flip-flop

Abstract: A digital circuit operable in a normal mode and in a test mode including memory elements which each operates as a static latch during the normal mode and operates as a dynamic master-slave flip-flop during the test mode. The digital circuit also includes combinational logic having a plurality of outputs, means operable in the normal mode to connect a combinational logic output to each of the inputs of the memory elements, and means operable in the test mode to connect outputs of memory elements to inputs of other memory elements so as to form a shift register to facilitate testing of complex digital circuits.

Universal masking on logic gate level

Abstract: A concept of random masking of arbitrary logic circuits on the logic gate level is developed and several techniques are proposed. The results are important for protecting hardware implementations of cryptographic algorithms against side-channel attacks.