Digital electronics

About: Digital electronics is a research topic. Over the lifetime, 10354 publications have been published within this topic receiving 153532 citations.

Quaternary Look-Up Tables Using Voltage-Mode CMOS Logic Design

Abstract: Data processing optimization is one of the main concerns for developing of multiple-valued logic. An advantage could be achieved by realization of new functions existing in non-binary logic. These new logic functions could be implemented using quaternary look-up tables. In this work, a quaternary multiplexer circuit is designed to implement any n-variable quaternary logic function based on its truth table. Voltage-mode CMOS with multi-threshold transistors and multi-Vdd quaternary design was suggested. The multiplexer circuit consists of quaternary down literal circuits, binary inverters and binary pass transistor gates. All circuits were simulated with the Spice tool using TSMC 0.18 mum technology and have shown improvements in performance and power consumption and using less transistors than their equivalent binary circuits.

A wafer scale integration neural network utilizing completely digital circuits

Abstract: A wafer scale integration (WSI) neural network utilizing completely digital circuits is reported. Three new technologies are used: (1) time-sharing digital bus; (2) efficient utilization of weight storage; and (3) redundant learning control circuit. Items 1 and 2 enable more than 500 neurons and effectively more than 30000 synapses to be fabricated on a 5-in silicon wafer. Item 3 enables a very high yield to be realized on one silicon wafer using a 0.8 mu m CMOS process. >

Software Assisted Digital RF Processor (DRP™) for Single-Chip GSM Radio in 90 nm CMOS

Abstract: This paper proposes and describes a new software and application programming interface view of an RF transceiver. It demonstrates benefits of using highly programmable digital control logic in an RF wireless system realized in a digital nanoscale CMOS process technology. It also describes a microprocessor architecture design in Digital RF Processor (DRPTM) and how it controls calibration and compensation for process, temperature and voltage variations of the analog and RF circuits to meet the required RF performance. A few calibration examples to reduce a DCO bias current and improve device reliability, as well as to optimize transmit modulation and receive performance, are given. The presented circuits and techniques have enabled successful implementation of a commercial single-chip GSM radio in 90 nm CMOS.

Design as you see FIT: system-level soft error analysis of sequential circuits

Abstract: Soft errors in combinational and sequential elements of digital circuits are an increasing concern as a result of technology scaling. Several techniques for gate and latch hardening have been proposed to synthesize circuits that are tolerant to soft errors. However, each such technique has associated overheads of power, area, and performance. In this paper, we present a new methodology to compute the failures in time (FIT) rate of a sequential circuit where the failures are at the system-level. System-level failures are detected by monitors derived from functional specifications. Our approach includes efficient methods to compute the FIT rate of combinational circuits (CFIT), incorporating effects of logical, timing, and electrical masking. The contribution of circuit components to the FIT rate of the overall circuit can be computed from the CFIT and probabilities of system-level failure due to soft errors in those elements. Designers can use this information to perform Pareto-optimal hardening of selected sequential and combinational components against soft errors. We present experimental results demonstrating that our analysis is efficient, accurate, and provides data that can be used to synthesize a low-overhead, low-FIT sequential circuit.