Digital electronics

About: Digital electronics is a research topic. Over the lifetime, 10354 publications have been published within this topic receiving 153532 citations.

Process monitor for CMOS integrated circuits

Abstract: A process for evaluating acceptability of a digital circuit having a first type of circuit element for a first change of state and a second type of circuit element for a second change of state, the process comprising: generating a leading edge of a first pulse with a pulse generation circuit formed on a substrate in common with the digital circuit and having elements of the first and the second type; generating a trailing edge of a first pulse with a pulse generation circuit formed on a substrate in common with the digital circuit and having elements of the first and the second type; generating an accepted-rejected signal, functionally related to the width of the pulse.

Self-assembling circuits with autonomous fault handling

Abstract: This paper reports on the results of our recent NASA SBIR contract, "Autonomous Self-Repairing Circuits," in which we developed a novel approach to fault-tolerant circuit synthesis utilizing a self-configurable hardware platform. The approach was based on the use of atomic components called Supercells. These Supercells perform several functions in the building of a desired target circuit: fault detection, fault isolation, configuration of new Supercells, determination of inter-cell wiring paths, and implementation of the final target circuit. By placing these tasks under the control of the Supercells themselves, the resulting system requires minimal external intervention. In particular, for a given target circuit, a fixed configuration string can be used to configure the system, regardless of the location of faults in the underlying hardware. This is because the configuration string does not directly implement the final circuit. Rather, it implements a self-organizing system, and that system then dynamically implements the desired target circuit.

Application of system-level EM modeling to high-speed digital IC packages and PCBs

Abstract: A system-level electromagnetic (EM) modeling tool combining a three-dimensional (3-D) full-wave finite-element EM-field analysis tool and a time-domain electric-circuit simulator is developed and applied to various geometries such as multilayer printed circuit boards (PCBs), signal lines embedded in a PCB or package, and split power-distribution network. Since the signal integrity is a primary concern of high-speed digital circuits, the noise distributions on various circuit planes are evaluated from the analysis. These noise distributions, often called voice maps, are utilized to identify the location of the major source of simultaneous switching noise (SSN). This information can eventually be adapted for optimum placement of decoupling capacitors to minimize the noise fluctuations on the various circuit planes on an entire PCB.

PROPAGATION DELAY IN HIGH SPEED SILICON BIPOLAR AND GaAs HBT DIGITAL CIRCUITS

Abstract: The needs for multi-gigabits/second digital electronics in advanced lightwave systems have motivated R & D for the next generation of high speed bipolar technology. The speed of the digital circuit may be estimated from the propagation delay of the logic gate. We discuss physics of the delay and show that it is fundamentally limited by the time needed for turning on (off) a transistor and by the time for charging (discharging) of capacitances in the circuit. We present a large-signal theory based on a charge-control model for the calculation of these limits. The results obtained for emitter coupled logic and current mode logic are used to analyze current technologies of silicon bipolar and GaAs HBTs.