scispace - formally typeset
Search or ask a question
Topic

Digital electronics

About: Digital electronics is a research topic. Over the lifetime, 10354 publications have been published within this topic receiving 153532 citations.


Papers
More filters
Proceedings ArticleDOI
10 Oct 2004
TL;DR: Three new reversible logic gates can be used to implement reversible digital circuits of various levels of complexity and provide on-line testability for circuits implemented using them.
Abstract: A technique for an on-line testable reversible logic circuit is presented. Three new reversible logic gates have been introduced in this paper. These gates can be used to implement reversible digital circuits of various levels of complexity. The major feature of these gates is that they provide on-line testability for circuits implemented using them. The application of these gates in implementation of a subset of MCNC benchmark circuits is provided.

43 citations

Journal ArticleDOI
TL;DR: The presented all-optical logic device is simple, compact and efficient, and can be applied to many other nano-photonic logic devices as well, thereby potentially offering useful guidelines for their designs and further applications in on-chip optical computing and optical interconnection networks.

43 citations

Journal ArticleDOI
TL;DR: This study proposes a QUSR with an extremely optimized area and latency, by connecting four 4-to-1 Muxes and a four-bit shift register, and proposes a new D flip-flop, and designs a shift register by connecting these.
Abstract: Quantum-dot cellular automata (QCA) represent an alternative technology for implementing various computations and high-performance, low-power consumption digital circuits at nanoscale. Meanwhile, an universal shift register (USR) with guaranteed free position shift and parallel input and transfer of the stored bit value of the register is an essential element in the design of the circuit. Therefore, we propose an USR circuit based on QCA (QUSR) which can be configured by combining the shift register with a multiplexer (Mux) to select the function of the register. In this study, we propose a 2-to-1 Mux based on the electronic correlations between the cells, and then extend this to a 4-to-1 Mux. We also propose a new D flip-flop, and design a shift register by connecting these. Finally, we propose a QUSR with an extremely optimized area and latency, by connecting four 4-to-1 Muxes and a four-bit shift register. The proposed QUSR is highly efficient, in terms of the space, time complexity and energy dissipation. All proposed structures are simulated by QCADesigner to demonstrate the clarity of the motion and efficiency. We also measured and compared the energy dissipation in three tunneling levels by QCAPro.

43 citations

Journal ArticleDOI
TL;DR: To evaluate the potentiality of GaAs MESFETs as transmitting gates, dynamic TT~ flip-flops have been fabricated using a self-aligned planar process, and speed improvement and topological simplification of fully static LSI subsystems are investigated.
Abstract: To evaluate the potentiality of GaAs MESFETs as transmitting gates, dynamic TT~ flip-flops have been fabricated using a self-aligned planar process. The maximum operating frequency is 10.2 GHz, which is the best speed performance ever reported for a digital circuit. The performance of the transmitting gates within the circuits are discussed in detail. Speed improvement and topological simplification of fully static LSI subsystems are investigated.

43 citations

Journal ArticleDOI
30 Apr 2012
TL;DR: Several simulations conducted using different voltage supplies, load capacitors and temperature variation demonstrate the superiority of the XOR (3T) based full adder designs in term of delay, power and power delay product (PDP) compared to the other fullAdder circuits.
Abstract: This paper presents comparative study of high-speed, low-power and low voltage full adder circuits. Our approach is based on XOR-XNOR design full adder circuits in a single unit. A low power and high performance 9T full adder cell using a design style called “XOR (3T)” is discussed. The designed circuit commands a high degree of regularity and symmetric higher density than the conventional CMOS design style as well as it lowers power consumption by using XOR (3T) logic circuits. Gate Diffusion Input (GDI) technique of low-power digital combinatorial circuit design is also described. This technique helps in reducing the power consumption and the area of digital circuits while maintaining low complexity of logic design. This paper analyses, evaluates and compares the performance of various adder circuits. Several simulations conducted using different voltage supplies, load capacitors and temperature variation demonstrate the superiority of the XOR (3T) based full adder designs in term of delay, power and power delay product (PDP) compared to the other full adder circuits. Simulation results illustrate the superiority of the designed adder circuits against the conventional CMOS, TG and Hybrid full adder circuits in terms of power, delay and power delay product (PDP).

43 citations


Network Information
Related Topics (5)
Electronic circuit
114.2K papers, 971.5K citations
92% related
Integrated circuit
82.7K papers, 1M citations
91% related
CMOS
81.3K papers, 1.1M citations
91% related
Transistor
138K papers, 1.4M citations
87% related
Semiconductor memory
45.4K papers, 663.1K citations
86% related
Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202369
2022156
2021171
2020255
2019255
2018250