Digital electronics

About: Digital electronics is a research topic. Over the lifetime, 10354 publications have been published within this topic receiving 153532 citations.

Multiple level associative logic circuits

Abstract: Disclosed are universal associative logic circuits for use in designing logic systems. The logic circuits comprise an array of logic elements interconnected in a preselected configuration to implement logic in factored and unfactored form by generating single Boolean functions and complex groups of such functions having single and multiple outputs through multiple levels of combinational logic providing electrical responses to signals applied to the circuit and to signals generated within the circuit. Sequential logic functions are generated by interconnecting the logic elements to form storage elements.

Formal verification of candidate solutions for post-synthesis evolutionary optimization in evolvable hardware

Abstract: We propose to utilize a formal verification algorithm to reduce the fitness evaluation time for evolutionary post-synthesis optimization in evolvable hardware. The proposed method assumes that a fully functional digital circuit is available. A post-synthesis optimization is then conducted using Cartesian Genetic Programming (CGP) which utilizes a satisfiability problem solver to decide whether a candidate solution is functionally correct or not. It is demonstrated that the method can optimize digital circuits of tens of inputs and thousands of gates. Furthermore, the number of gates was reduced for the LGSynth93 benchmark circuits by 37.8% on average with respect to results of the conventional SIS tool.

Logic Verification Algorithms and their Parallel Implementation

Abstract: LOVER incorporates a novel approach to combinational logic verification and obtains good results when compared to existing techniques. In this paper we describe a new verification algorithm, LOVER-PODEM, whose enumeration phase is based on PODEM. A variant of LOVER-PODEM, called PLOVER, is presented. We have developed, for the first time, parallel logic verification schemes. Issues in efficiently parallelizing both general and specific LOVER-based approaches to logic verification over a large number of processors are addressed. We discuss parallelism inherent in the LOVER framework regardless of what enumeration and simulation algorithms are used. Since the enumeration phase is the efficiency bottleneck in parallelizing LOVER-based approaches, we have developed parallel versions of PODEM-based enumeration algorithms. Experimental results are presented to show that high processor utilization can be achieved when these parallelisms are exploited. Speed-up factors of over 7.8 have been achieved with 8 processor configurations.

Ultralow-Power Operation in Subthreshold Regimes Applying Clockless Logic

Abstract: Energy performance requirements are causing designers of next-generation systems to explore approaches to lowest possible power consumption Subthreshold operation is being examined to stretch low-power circuit designs beyond the normal modes of operation, with the potential for large energy savings Some of the challenges to be overcome, like 10-100× performance penalties, are being addressed by research into parallelism However, the uncertainty in timing generated by operating in subthreshold represents a major challenge to overcome In this paper, first, we will introduce some background information on digital logic subthreshold operation, then provide some background on clockless logic design approaches giving a brief overview of some of the characteristics of the different design styles and focusing on NULL convention logic Next, we will examine the application of that clockless logic approach to a military system, reviewing the background of the experiment, factors considered in the comparison, and then summarizing the results of the comparisons Finally, an overview of additional research and development that will be needed to make the technique available to subthreshold designers is presented