Digital electronics

About: Digital electronics is a research topic. Over the lifetime, 10354 publications have been published within this topic receiving 153532 citations.

A wafer-scale digital integrator using restructurable VSLI

Abstract: Wafer-scale integration has been demonstrated by fabricating a digital integrator on a monolithic 20-cm2silicon chip, the first laser-restructured digital logic system. Large-area integration is accomplished by laser programming of metal interconnect for defect avoidance. This paper describes the technology for laser welding and cutting, the design methodology and CAD tools developed for wafer-scale integration, and the integrator itself.

Field Programmable Logic Gates Using GMR Devices

Abstract: This paper summarizes the basic methodology for building field programmable logic functions using GMR devices. The size of the gates and the properties of the sense amplifier are a function of the particular GMR technology used, device matching and the magnitude of the sense current available. A test chip is currently in fabrication.

Programmable digital circuits

Abstract: A composite digital network including an integrating circuit, a summing circuit and a coefficient circuit is formed as an integrated circuit that provides a selected one of digital arithmetic circuits that perform different arithmetic operations depending upon coefficients of the coefficient circuits. A plurality of units of such composite digital networks may be connected in rows, columns or layers to provide an expanded network. In a method of producing such a composite digital network, basic digital arithmetic circuits that respectively correspond to various types of basic analog arithmetic circuits are defined based on Kirchhoff's rules, for example, and these basic digital arithmetic circuits are coupled to each other via a coefficient circuit to thus provide a generic digital arithmetic integrated circuit.

Complementary Resistive Switch-Based Arithmetic Logic Implementations Using Material Implication

Abstract: Memristors are considered among the most promising future building blocks of next-generation digital systems. This paper focuses on specific ways to implement logic and arithmetic unit using memristors. In particular, we present a set of complementary resistive switching (CRS)-based stateful logic operations that use material implication to provide the basic logic functionalities needed to realize logic circuits. The proposed solution benefits from the exponential reduction in sneak path current in crossbar implemented logic. This paper also presents a closed-form expression for sneak current and analyzes the impact of device variation on the behavior of the proposed logic blocks. Our technique, as other similar techniques proposed in the literature, requires several sequential steps to perform the computation. However, in this paper, we show that only three steps are required for implementing N input nand gate, whereas previously proposed memristor-based stateful logic needs N + 1 steps. We validated the effectiveness of our solution through cadence spectre circuit simulator on a number of logic circuits. Finally, we extended this approach for arithmetic circuits with an 8-bit adder and a 4-bit multiplier.

Modeling and Mitigating Transient Errors in Logic Circuits

Abstract: Transient or soft errors caused by various environmental effects are a growing concern in micro and nanoelectronics. We present a general framework for modeling and mitigating the logical effects of such errors in digital circuits. We observe that some errors have time-bounded effects; the system's output is corrupted for a few clock cycles, after which it recovers automatically. Since such erroneous behavior can be tolerated by some applications, i.e., it is noncritical at the system level, we define the critical soft error rate (CSER) as a more realistic alternative to the conventional SER measure. A simplified technology-independent fault model, the single transient fault (STF), is proposed for efficiently estimating the error probabilities associated with individual nodes in both combinational and sequential logic. STFs can be used to compute various other useful metrics for the faults and errors of interest, and the required computations can leverage the large body of existing methods and tools designed for (permanent) stuck-at faults. As an application of the proposed methodology, we introduce a systematic strategy for hardening logic circuits against transient faults. The goal is to achieve a desired level of CSER at minimum cost by selecting a subset of nodes for hardening against STFs. Exact and approximate algorithms to solve the node selection problem are presented. The effectiveness of this approach is demonstrated by experiments with the ISCAS-85 and -89 benchmark suites, as well as some large (multimillion-gate) industrial circuits.