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Digital electronics

About: Digital electronics is a research topic. Over the lifetime, 10354 publications have been published within this topic receiving 153532 citations.


Papers
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Journal ArticleDOI
TL;DR: Experimental results demonstrate that the proposed 32-bit adder can reduce power dissipation of conventional low-power adders for practical multimedia applications and can be utilized in other adder cells to compromise complexity, speed and power consumption for application-specific integrated circuits and digital signal processors.
Abstract: To design a power-efficient digital signal processor, this study develops a fundamental arithmetic unit of a low-power adder that operates on effective dynamic data ranges. Before performing an addition operation, the effective dynamic ranges of two input data are determined. Based on a larger effective dynamic range, only selected functional blocks of the adder are activated to generate the desired result while the input bits of the unused functional blocks remain in their previous states. The added result is then recovered to match the required word length. Using this approach to reduce switching operations of noneffective bits allows input data in 2's complement and sign magnitude representations to have similar switching activities. This investigation thus proposes a 2's complement adder with two master-stage and slave-stage flip-flops, a dynamic-range determination unit and a sign-extension unit, owing to the easy implementation of addition and subtraction in such a system. Furthermore, this adder has a minimum number of transistors addressed by carry-in bits and thus is designed to reduce the power consumption of its unused functional blocks. The dynamic range and sign-extension units are explored in detail to minimize their circuit area and power consumption. Experimental results demonstrate that the proposed 32-bit adder can reduce power dissipation of conventional low-power adders for practical multimedia applications. Besides the ripple adder, the proposed approach can be utilized in other adder cells, such as carry lookahead and carry-select adders, to compromise complexity, speed and power consumption for application-specific integrated circuits and digital signal processors.

41 citations

Book
01 Jan 1968
TL;DR: The fifth edition of Digital Principles and Applications is completely reorganized and is written for the individual who wishes to learn the principles of digital circuits and then apply them to useful, meaningful designs.
Abstract: From the Publisher: The fifth edition of Digital Principles and Applications is completely reorganized . It is written for the individual who wishes to learn the principles of digital circuits and then apply them to useful, meaningful designs. The material in this book is appropriate for an introductory course in digital logic in either a computer or an electronics program. It is also appropriate for 'self-study' and as a 'reference' for individuals working in the field.

41 citations

Proceedings ArticleDOI
22 Mar 2009
TL;DR: Experimental demonstration of a concept of subcarrier modulation with the symbol rate and carrier frequency being identical, and thereby synchronous, with 2.5 Gsymbols/s signals generated with binary digital electronics.
Abstract: We report experimental demonstration of a concept of subcarrier modulation with the symbol rate and carrier frequency being identical, and thereby synchronous. The concept is demonstrated with 2.5 Gsymbols/s signals generated with binary digital electronics.

41 citations

Journal ArticleDOI
TL;DR: A new approach for generating test vectors, using test cultivation, for both combinational and sequential VLSI circuits described hierarchically at the transistor, gate, and higher levels is discussed, reducing the memory requirements and allowing test generation for large circuits.
Abstract: This paper discusses a new approach for generating test vectors, using test cultivation, for both combinational and sequential VLSI circuits described hierarchically at the transistor, gate, and higher levels. The approach is based on continuous mutation of a given input sequence and on analyzing the mutated vectors for selecting the test set. The hierarchical technique used in the analysis drastically reduces the memory requirements, allowing test generation for large circuits. The test cultivation algorithms are simulation-based and a test set can be cultivated for any circuit that can be simulated logically. In particular, general MOS digital designs can be handled, and both stuck-at and transistor faults can be accurately modeled. Using the approach, tests were generated with very high fault coverage for gate-level circuits as well as for transistor level circuits.

41 citations

Proceedings ArticleDOI
18 Mar 2010
TL;DR: This paper demonstrates the feasibility of further reducing the analog circuit content of a radio receiver, while maintaining acceptable performance.
Abstract: Previous work [1,2] has demonstrated the feasibility of a drastic reduction of the analog circuits content in radio transmitters and synthesizers, in favour of more digital circuits. But for radio receivers, a major amount of analog circuitry is still required [1,3]. This paper demonstrates the feasibility of further reducing the analog circuit content of a radio receiver, while maintaining acceptable performance. The circuit offers the main advantages of a digital design: after adding one (small) macroblock to a digital standard-cell library, the whole receiver can be described in an RTL language and can be realised with a standard digital design methodology. Porting or scaling to another silicon technology becomes relatively easy.

41 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202369
2022156
2021171
2020255
2019255
2018250