Digital electronics

About: Digital electronics is a research topic. Over the lifetime, 10354 publications have been published within this topic receiving 153532 citations.

Equivalence of memory to Random Logic

Abstract: A model of the design process for computer logic is used to estimate the number of bits of memory required to replace a so-called "random logic" circuit. The model can also be used to compare the respective time delays of array logic and random logic.

Improved algorithmic methods for the prediction of wavefront propagation behavior in multiconductor transmission lines for high frequency digital signal processors

Abstract: Several computer-aided design (CAD) tools suitable for use by the designers of digital signal and data processors based on the quasi-TEM assumption for multiconductor transmission lines are presented. The integral equation method due to C. Wei, et al. (1984) is selected for the evaluation of electrostatic parameters, including capacitance, inductance, conductance, and resistance matrices, and attenuation factors as well as propagation constants and crosstalk. These parameters are thereafter used to simulate the waveforms of coupled stripline/microstrip lines by the system decoupling method, which is derived in a manner simpler than previously described in the literature. The computer codes along with the graphics input routines have been integrated into a CAD system referred to as MagiCAD, and are suitable for direct use in CAD procedures for the design of high-clock-rate digital circuits. Numerical examples, comparisons, and applications are shown. >

A 660 MB/s interface megacell portable circuit in 0.3 /spl mu/m-0.7 /spl mu/m CMOS ASIC

Abstract: A high-speed interface circuit delivering 660 MB/s data is implemented as a byte-wide I/O bus-interface cell. The interface contains low-swing input receivers, controlled-current output drivers, and clock-recovery circuits. The circuits perform well in noisy environments such as microprocessors, and withstand LdI/dt noise generated in high-inductance packages such as PQFPs. The interface is implemented as a full-custom ASIC library mega-cell, reducing area and power over gate-array approaches. An advanced CAD methodology is used to easily port the analog circuits and high-speed digital circuits in the interface cell to multiple-fabrication process technologies. The cell is used as an interface for ASIC-to-DRAM communication and for ASIC-to-ASIC communication, for point-to-point links and for bused links.

Global flow optimization in automatic logic design

Abstract: A method for optimizing digital logic networks is described This approach uses the techniques of global flow analysis to efficiently gather information about the relationship between different wires in a circuit and uses methods from network flow to use this information to optimize the circuit It differs from earlier methods for optimization of multilevel logic networks in that valid rearrangements of signal connections depend on the maintenance of global circuit invariants An algorithm which reduces the problem of finding small circuits in this equivalence class to the problem of finding a min-cut in an associated graph is described This algorithm has been implemented and forms part of an automatic design system in use within IBM The authors describe the results of experiments undertaken to evaluate the effect of the techniques >

Implementation of Basic Arithmetic Operations Using Cellular Automaton

Abstract: This paper presents hardware architecture to perform the basic arithmetic operation addition using cellular automata (CA). This age old problem of addition were previously solved by ripple circuit or carry look ahead circuit or by using a combination of them. Each of these circuits is purely combinational in nature and their complexity is centered on the number of logic gates and the associated gate delays. On the contrary, in our CA based design the complexity is mainly centered on the number of clock cycles required to finish the computation instead of the gate delays.