Digital electronics

About: Digital electronics is a research topic. Over the lifetime, 10354 publications have been published within this topic receiving 153532 citations.

A highly flexible sea-of-gates structure for digital and analog applications

Abstract: A sea-of-gates structure optimized for digital random logic applications as well as for regular arrays and analog circuits is described. Associated with a dedicated design procedure and a systematic metallization strategy, the structure features a full cell-abutment capability and true channelless routing. After reviewing the advantages and limitations of currently available arrays, the main characteristics of the array architecture are presented, and applications to different circuit families are detailed. Design automation tools suited to the structure and design methodology are reviewed. Design results and performance are presented for several macroblocks and are compared with other semicustom approaches. A set of rules which allows an automatic transformation of the sea-of-gates layout into a topologically equivalent full-custom layout, converting semicustom prototypes to full-performance circuits, is presented. >

A practical floating-gate Muller-C element using vMOS threshold gates

Abstract: This paper presents the rationale for vMOS-based realizations of digital circuits when logic design techniques based on threshold logic gates are used. Some practical problems in the vMOS implementation of threshold gates have been identified and solved. The feasibility and versatility of the proposed technique as well as its potential as a low-cost design technique for CMOS technologies have been shown by experimental results from a multiple-input Muller C-element. The proposed new realization exhibits better performance related to delay and area and power consumption than the traditional logic implementation.

Microprocessor sensitivity to failures: control vs. execution and combinational vs. sequential logic

Abstract: The goal of this study is to characterize the impact of soft errors on embedded processors. We focus on control versus speculation logic on one hand, and combinational versus sequential logic on the other. The target system is a gate-level implementation of a DLX-like processor. The synthesized design is simulated, and transients are injected to stress the processor while it is executing selected applications. Analysis of the collected data shows that fault sensitivity of the combinational logic (4.2% for a fault duration of one clock cycle) is not negligible, even though it is smaller than the fault sensitivity of flip-flops (10.4%). Detailed study of the error impact, measured at the application level, reveals that errors in speculation and control blocks collectively contribute to about 34% of crashes, 34% of fail-silent violations and 69% of application incomplete executions. These figures indicate the increasing need for processor-level detection techniques over generic methods, such as ECC and parity, to prevent such errors from propagating beyond the processor boundaries.

Analysis of the impact of proximity correction algorithms on circuit performance

Abstract: Variation in channel length degrades circuit reliability and yield. A common way to compensate for this problem is to increase the mean channel length, which, unfortunately, degrades circuit performance for digital circuits. One source of channel length variation is lithography, during which the line width is influenced by local layout patterns. It is possible to compensate for this effect by resizing transistor gates appropriately on the mask. However, the effectiveness of the correction is limited by constraints such as the mask correction resolution. To determine how to design a good correction scheme with limited resources, we have developed a method to compare different correction algorithms in terms of their impact on the performance of one of the main functional blocks in a state-of-the-art microprocessor. In particular, to evaluate correction algorithms while avoiding the high cost associated with generating multiple mask sets and fabricating product wafers with each of these mask sets, we present a method for predicting the correction results using simulation. Our methodology involves a DRC-based approach for gate resizing, along with critical path simulation for evaluating circuit performance. In-line CD measurement data were used to measure the impact of the proximity effect on transistor channel length. Electrical test results were used to calibrate the device models for circuit simulation.

On Minimally Testable Logic Networks

Abstract: A new technique to modify any logic network to facilitate diagnosis is given. By providing extra controllable inputs (at most six) and observable outputs it is shown that any number of stuck-at-faults in a logic network can be detected by applying only three tests. This number is believed to be minimal for networks using current technologies. Example of logic module that can be used to realize any logic function such that only two tests detect stuck-at-faults is also given.